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Compensation of IQ imbalance and phase noise in OFDM systems

IEEE transactions on wireless communications, 2005-05, Vol.4 (3), p.872-877

2005

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Space-time block coding for single-carrier block transmission DS-CDMA downlink

IEEE journal on selected areas in communications, 2003-04, Vol.21 (3), p.350-361

2003

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Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

IEEE journal of solid-state circuits, 2002-08, Vol.37 (8), p.1065-1072

2002

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Background memory area estimation for multidimensional signal processing systems

IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.157-172

1995

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Reed-solomon codes implementing a coded single-carrier with cyclic prefix scheme

IEEE transactions on communications, 2009-04, Vol.57 (4), p.1031-1038

2009

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Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings

IEEE transactions on very large scale integration (VLSI) systems, 1998-12, Vol.6 (4), p.529-537

1998

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Spatial-Mode Selection for the Joint Transmit and Receive MMSE Design

EURASIP Journal on Applied Signal Processing, 2004-12, Vol.2004 (9), p.746413-1211, Article 746413

2004

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ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Field Programmable Logic and Application, 2003, p.61-70

2003

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OFDM versus Single Carrier: A Realistic Multi-Antenna Comparison

EURASIP Journal on Applied Signal Processing, 2004-08, Vol.2004 (9), p.320840-1287, Article 320840

2004

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Minimizing the required memory bandwidth in VLSI system realizations

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.433-441

1999

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Multicarrier Block-Spread CDMA for Broadband Cellular Downlink

EURASIP Journal on Applied Signal Processing, 2004-08, Vol.2004 (10), p.354827-1584, Article 354827

2004

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SWAN: high-level simulation methodology for digital substrate noise generation

IEEE transactions on very large scale integration (VLSI) systems, 2006-01, Vol.14 (1), p.23-33

2006

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Multicarrier Block-Spread CDMA for Broadband Cellular Downlink

EURASIP journal on advances in signal processing, 2004-09, Vol.2004 (10), p.354827-354827

2004

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Spatial-Mode Selection for the Joint Transmit and Receive MMSE Design

EURASIP journal on advances in signal processing, 2004-08, Vol.2004 (9), p.746413-746413

2004

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Strategy for power-efficient design of parallel systems

IEEE transactions on very large scale integration (VLSI) systems, 1999-06, Vol.7 (2), p.258-265

1999

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An efficient VLSI architecture for 2-D wavelet image coding with novel image scan

IEEE transactions on very large scale integration (VLSI) systems, 1999-03, Vol.7 (1), p.56-68

1999

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A combined OFDM/SDMA approach

IEEE journal on selected areas in communications, 2000-11, Vol.18 (11), p.2312-2321

2000

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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.399-404

2002

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TRANSFORMATION OF NESTED LOOPS WITH MODULO INDEXING TO AFFINE RECURRENCES

Parallel processing letters, 1994-09, Vol.4 (3), p.271-280

1994

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Ambient intelligence: gigascale dreams and nanoscale realities

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.29-35 Vol. 1

De Man, H.

2005

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Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-02, Vol.16 (2), p.133-145

1997

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Evolution of substrate noise generation mechanisms with CMOS technology scaling

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-02, Vol.53 (2), p.296-305

2006

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1383-1395

2002

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Adaptive loading for OFDM/SDMA-based wireless networks

IEEE transactions on communications, 2002-11, Vol.50 (11), p.1798-1810

2002

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Efficient computation of symbol statistics from bit a priori information in turbo receivers

IEEE transactions on communications, 2009-07, Vol.57 (7), p.1889-1891

2009

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Compensation of IQ imbalance and phase noise in OFDM systems

Space-time block coding for single-carrier block transmission DS-CDMA downlink

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

Background memory area estimation for multidimensional signal processing systems

Reed-solomon codes implementing a coded single-carrier with cyclic prefix scheme

Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings

Spatial-Mode Selection for the Joint Transmit and Receive MMSE Design

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

OFDM versus Single Carrier: A Realistic Multi-Antenna Comparison

Minimizing the required memory bandwidth in VLSI system realizations

Multicarrier Block-Spread CDMA for Broadband Cellular Downlink

SWAN: high-level simulation methodology for digital substrate noise generation

Multicarrier Block-Spread CDMA for Broadband Cellular Downlink

Spatial-Mode Selection for the Joint Transmit and Receive MMSE Design

Strategy for power-efficient design of parallel systems

An efficient VLSI architecture for 2-D wavelet image coding with novel image scan

A combined OFDM/SDMA approach

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

TRANSFORMATION OF NESTED LOOPS WITH MODULO INDEXING TO AFFINE RECURRENCES

Ambient intelligence: gigascale dreams and nanoscale realities

Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing

Evolution of substrate noise generation mechanisms with CMOS technology scaling

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

Adaptive loading for OFDM/SDMA-based wireless networks

Efficient computation of symbol statistics from bit a priori information in turbo receivers

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