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Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU–GPU platforms

Journal of real-time image processing, 2020-10, Vol.17 (5), p.1567-1583

2020

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Moving Towards and Reaching a 3-D Target by Embodied Guidance: Parsimonious Vs Explicit Sound Metaphors

Lecture Notes in Computer Science, 2023, Vol.14020, p.229-243

2023

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A domain-specific high-level programming model

Concurrency and computation, 2016-03, Vol.28 (3), p.750-767

2016

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Efficient implementation of data flow graphs on multi-gpu clusters

Journal of real-time image processing, 2014-03, Vol.9 (1), p.217-232

2014

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A Visual Programming Model to Implement Coarse-Grained DSP Applications on Parallel and Heterogeneous Clusters

Euro-Par 2014: Parallel Processing Workshops, p.141-152

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Efficient implementation of data flow graphs on multi-gpu clusters: Design and Architectures of Real-Time Image Processing in Embedded Systems

Journal of real-time image processing, 2014, Vol.9 (1), p.217-232

2014

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Comparative Study of Natural Replay and Experience Replay in Online Object Detection

2023 IEEE/CVF International Conference on Computer Vision Workshops (ICCVW), 2023, p.3587-3595

2023

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Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

IEEE transactions on very large scale integration (VLSI) systems, 2008-11, Vol.16 (11), p.1454-1464

2008

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Online Class Incremental Learning with One-Vs-All Classifiers for Resource Constrained Devices

2023 International Symposium on Image and Signal Processing and Analysis (ISPA), 2023, p.1-6

2023

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SysCellC: a data-flow programming model on multi-GPU

Procedia computer science, 2010-05, Vol.1 (1), p.1035-1044

2010

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Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection

2018 IEEE 5th International Congress on Information Science and Technology (CiSt), 2018, p.308-312

2018

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Performance and Scalability Improvement of GMM Background Segmentation Algorithm on Multi-core Parallel Platforms

Proceedings of the 1st International Conference on Electronic Engineering and Renewable Energy, p.120-127

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Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection

2018 4th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2018, p.1-5

2018

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SignalPU: A Programming Model for DSP Applications on Parallel and Heterogeneous Clusters

2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS), 2014, p.937-944

2014

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Task migration of DSP application specified with a DFG and implemented with the BSP computing model on a CPU-GPU cluster

2013 Conference on Design and Architectures for Signal and Image Processing, 2013, p.326-333

2013

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A Programming Model and a NoC-Based Architecture for Streaming Applications

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010, p.393-397

2010

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DFG implementation on multi GPU cluster with computation-communication overlap

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), 2011, p.1-8

2011

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SysCellC: SystemC on Cell

2008 International Conference on Computational Sciences and Its Applications, 2008, p.234-244

2008

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A Computation Core for Communication Refinement of Digital Signal Processing Algorithms

9th EUROMICRO Conference on Digital System Design (DSD'06), 2006, p.240-250

2006

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Design exploration and HW/SW rapid prototyping for real-time system design

16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 2005, p.240-242

2005

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Pipelined memory controllers for DSP applications handling unpredictable data accesses

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005, p.268-269

2005

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C-based rapid prototyping for digital signal processing

13th European Signal Processing Conference (EUSIPCO 2005), 2005, p.1-4

2005

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A Receptor Pair with an Integrated Decoy Converts Pathogen Disabling of Transcription Factors to Immunity

Cell, 2015-05, Vol.161 (5), p.1074-1088

2015

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The effect of room temperature ionic liquids on the selective biocatalytic hydrolysis of chitin via sequential or simultaneous strategies

Green chemistry : an international journal and green chemistry resource : GC, 2017, Vol.19 (17), p.4122-4131

2017

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Management and prevention of anemia (acute bleeding excluded) in adult critical care patients

Annals of intensive care, 2020-07, Vol.10 (1), p.97-97, Article 97

2020

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Efficient adaptive load balancing approach for compressive background subtraction algorithm on heterogeneous CPU–GPU platforms

Moving Towards and Reaching a 3-D Target by Embodied Guidance: Parsimonious Vs Explicit Sound Metaphors

A domain-specific high-level programming model

Efficient implementation of data flow graphs on multi-gpu clusters

A Visual Programming Model to Implement Coarse-Grained DSP Applications on Parallel and Heterogeneous Clusters

Efficient implementation of data flow graphs on multi-gpu clusters: Design and Architectures of Real-Time Image Processing in Embedded Systems

Comparative Study of Natural Replay and Experience Replay in Online Object Detection

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

Online Class Incremental Learning with One-Vs-All Classifiers for Resource Constrained Devices

SysCellC: a data-flow programming model on multi-GPU

Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection

Performance and Scalability Improvement of GMM Background Segmentation Algorithm on Multi-core Parallel Platforms

Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection

SignalPU: A Programming Model for DSP Applications on Parallel and Heterogeneous Clusters

Task migration of DSP application specified with a DFG and implemented with the BSP computing model on a CPU-GPU cluster

A Programming Model and a NoC-Based Architecture for Streaming Applications

DFG implementation on multi GPU cluster with computation-communication overlap

SysCellC: SystemC on Cell

A Computation Core for Communication Refinement of Digital Signal Processing Algorithms

Design exploration and HW/SW rapid prototyping for real-time system design

Pipelined memory controllers for DSP applications handling unpredictable data accesses

C-based rapid prototyping for digital signal processing

A Receptor Pair with an Integrated Decoy Converts Pathogen Disabling of Transcription Factors to Immunity

The effect of room temperature ionic liquids on the selective biocatalytic hydrolysis of chitin via sequential or simultaneous strategies

Management and prevention of anemia (acute bleeding excluded) in adult critical care patients

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