UB Paderborn / Katalog / Suche / in CDI

Compatible Equivalence Checking of X-Valued Circuits

2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, p.1-9

2021

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Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach

Journal of the Chinese Institute of Engineers, 2016-11, Vol.39 (8), p.977-985

2016

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Adaptive interpolation-based model checking

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, p.744-749

2014

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Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-03, Vol.32 (3), p.467-478

2013

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A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-01, Vol.33 (1), p.139-152

2014

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Robust Qubit Mapping Algorithm via Double-Source Optimal Routing on Large Quantum Circuits

ACM transactions on quantum computing (Print), 2024-08

2024

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To SAT or Not to SAT: Scalable Exploration of Functional Dependency

IEEE transactions on computers, 2010-04, Vol.59 (4), p.457-467

2010

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An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-06, Vol.32 (6), p.928-939

2013

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Symbolic model checking on SystemC designs

DAC Design Automation Conference 2012, 2012, p.327-333

2012

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Conquering the scheduling alternative explosion problem of SystemC symbolic simulation

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, p.685-690

2013

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A robust functional ECO engine by SAT proof minimization and interpolation techniques

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010, p.729-734

2010

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A robust general constrained random pattern generator for constraints with variable ordering

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012, p.109-114

2012

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A robust constraint solving framework for multiple constraint sets in constrained random verification

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-7

2013

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Interpolation-based incremental ECO synthesis for multi-error logic rectification

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.146-151

2011

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Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction

Proceedings of the Conference on Design, Automation and Test in Europe, 2012, p.1567-1572

2012

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Using SAT-based Craig interpolation to enlarge clock gating functions

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.621-626

2011

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A counterexample-guided interpolant generation algorithm for SAT-based model checking

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-6

2013

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A false-path aware formal static timing analyzer considering simultaneous input transitions

2009 46th ACM/IEEE Design Automation Conference, 2009, p.25-30

2009

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SAT-controlled redundancy addition and removal: a novel circuit restructuring technique

Proceedings of the 2009 Asia and South Pacific Design Automation Conference, 2009, p.191-196

2009

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Formal deadlock checking on high-level SystemC designs

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2010, p.794-799

2010

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Match and replace: a functional ECO engine for multi-error circuit rectification

Proceedings of the International Conference on Computer-Aided Design, 2011, p.383-388

2011

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Property-specific sequential invariant extraction for SAT-based unbounded model checking

Proceedings of the International Conference on Computer-Aided Design, 2011, p.674-678

2011

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Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques

Proceedings of the International Conference on Computer-Aided Design, 2011, p.602-607

2011

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QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification

Tools and Algorithms for the Construction and Analysis of Systems, p.377-391

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Automatic abstraction refinement of TR for PDR

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 2016, p.121-126

2016

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Compatible Equivalence Checking of X-Valued Circuits

Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach

Adaptive interpolation-based model checking

Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification

A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification

Robust Qubit Mapping Algorithm via Double-Source Optimal Routing on Large Quantum Circuits

To SAT or Not to SAT: Scalable Exploration of Functional Dependency

An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation

Symbolic model checking on SystemC designs

Conquering the scheduling alternative explosion problem of SystemC symbolic simulation

A robust functional ECO engine by SAT proof minimization and interpolation techniques

A robust general constrained random pattern generator for constraints with variable ordering

A robust constraint solving framework for multiple constraint sets in constrained random verification

Interpolation-based incremental ECO synthesis for multi-error logic rectification

Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction

Using SAT-based Craig interpolation to enlarge clock gating functions

A counterexample-guided interpolant generation algorithm for SAT-based model checking

A false-path aware formal static timing analyzer considering simultaneous input transitions

SAT-controlled redundancy addition and removal: a novel circuit restructuring technique

Formal deadlock checking on high-level SystemC designs

Match and replace: a functional ECO engine for multi-error circuit rectification

Property-specific sequential invariant extraction for SAT-based unbounded model checking

Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques

QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification

Automatic abstraction refinement of TR for PDR

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