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Architecture of Cobweb-Based Redundant TSV for Clustered Faults

IEEE transactions on very large scale integration (VLSI) systems, 2020-07, Vol.28 (7), p.1736-1739

2020

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Low-overhead TRNG based on MUX for cryptographic protection using multiphase sampling

The Journal of supercomputing, 2023-10, Vol.79 (15), p.17170-17186

2023

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LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

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Methyl gallate: Review of pharmacological activity

Pharmacological research, 2023-08, Vol.194, p.106849-106849, Article 106849

2023

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Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

IEEE transactions on very large scale integration (VLSI) systems, 2017-06, Vol.25 (6), p.1978-1982

2017

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High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

IEEE transactions on circuits and systems. I, Regular papers, 2021-02, Vol.68 (2), p.741-750

2021

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Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

IEEE transactions on circuits and systems. II, Express briefs, 2020-11, Vol.67 (11), p.2657-2661

2020

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URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators

The Journal of supercomputing, 2023-09, Vol.79 (13), p.14827-14847

2023

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Semi-polar (11–22) GaN epitaxial films with significantly reduced defect densities grown on m-plane sapphire using a sequence of two in situ SiNx interlayers

Applied physics letters, 2019-04, Vol.114 (13)

2019

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High-performance, low-cost, and highly reliable radiation hardened latch design

Electronics letters, 2016-01, Vol.52 (2), p.139-141

2016

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Whole-exome mutational landscape and molecular marker study in mucinous and clear cell ovarian cancer cell lines 3AO and ES2

BMC cancer, 2023-04, Vol.23 (1), p.321-321, Article 321

2023

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Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems

Journal of electronic testing, 2021-08, Vol.37 (4), p.545-559

2021

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DBU-PG: energy-efficient noc design using dual-buffering power gating

The Journal of supercomputing, 2024, Vol.80 (10), p.13632-13656

2024

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Design of approximate Booth multipliers based on error compensation

Integration (Amsterdam), 2023-05, Vol.90, p.183-189

2023

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A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

IEEE transactions on nuclear science, 2016-12, Vol.63 (6), p.2985-2992

2016

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High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator

ACM transactions on reconfigurable technology and systems, 2023-12, Vol.16 (4), p.1-23, Article 64

2023

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A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design

Journal of electronic testing, 2022-02, Vol.38 (1), p.63-76

2022

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Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch

IEEE access, 2021, Vol.9, p.113622-113630

2021

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A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC

IEEE access, 2020, Vol.8, p.22650-22663

2020

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Impact of 3D growth and SiN x interlayer on the quality of (11–22) semi-polar GaN grown on m -plane sapphire

Applied physics express, 2019-11, Vol.12 (11), p.115501

2019

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DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip

Journal of electronic testing, 2019-12, Vol.35 (6), p.767-777

2019

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Jitter-Quantizing-Based TRNG Robust Against PVT Variations

IEEE access, 2020, Vol.8, p.108482-108490

2020

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Methyl Gallate Suppresses the Migration, Invasion, and Epithelial-Mesenchymal Transition of Hepatocellular Carcinoma Cells via the AMPK/NF-κB Signaling Pathway in vitro and in vivo

Frontiers in pharmacology, 2022-06, Vol.13, p.894285-894285

2022

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A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

IEICE transactions on electronics, 2015, Vol.E98.C (12), p.1171-1178

2015

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Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Architecture of Cobweb-Based Redundant TSV for Clustered Faults

Low-overhead TRNG based on MUX for cryptographic protection using multiphase sampling

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Methyl gallate: Review of pharmacological activity

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

URMP: using reconfigurable multicast path for NoC-based deep neural network accelerators

Semi-polar (11–22) GaN epitaxial films with significantly reduced defect densities grown on m-plane sapphire using a sequence of two in situ SiNx interlayers

High-performance, low-cost, and highly reliable radiation hardened latch design

Whole-exome mutational landscape and molecular marker study in mucinous and clear cell ovarian cancer cell lines 3AO and ES2

Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems

DBU-PG: energy-efficient noc design using dual-buffering power gating

Design of approximate Booth multipliers based on error compensation

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator

A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design

Design of a Highly Robust Triple-Node-Upset Self-Recoverable Latch

A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC

Impact of 3D growth and SiN x interlayer on the quality of (11–22) semi-polar GaN grown on m -plane sapphire

DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip

Jitter-Quantizing-Based TRNG Robust Against PVT Variations

Methyl Gallate Suppresses the Migration, Invasion, and Epithelial-Mesenchymal Transition of Hepatocellular Carcinoma Cells via the AMPK/NF-κB Signaling Pathway in vitro and in vivo

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

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