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Multiple-Wearable-Sensor-Based Gait Classification and Analysis in Patients with Neurological Disorders

Sensors (Basel, Switzerland), 2018-10, Vol.18 (10), p.3397

2018

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Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA

IEEE transactions on instrumentation and measurement, 2009-07, Vol.58 (7), p.2300-2315

2009

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IEEE_Xplore

Machine Learning-Based Detection Method for Wafer Test Induced Defects

IEEE transactions on semiconductor manufacturing, 2021-05, Vol.34 (2), p.161-167

2021

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IEEE_Xplore

Wafer Defect Pattern Labeling and Recognition Using Semi-Supervised Learning

IEEE transactions on semiconductor manufacturing, 2022-05, Vol.35 (2), p.291-299

2022

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IEEE_Xplore

Fault-Aware Dependability Enhancement Techniques for Flash Memories

IEEE transactions on very large scale integration (VLSI) systems, 2020-03, Vol.28 (3), p.634-645

2020

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IEEE_Xplore

Surface EMG vs. High-Density EMG: Tradeoff Between Performance and Usability for Head Orientation Prediction in VR Application

IEEE access, 2021, Vol.9, p.45418-45427

2021

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Fault-Aware Dependability Enhancement Techniques for Phase Change Memory

Journal of electronic testing, 2021-08, Vol.37 (4), p.503-513

2021

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Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application

IEEE transactions on instrumentation and measurement, 2009-06, Vol.58 (6), p.1897-1906

2009

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IEEE_Xplore

Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM

Journal of electronic testing, 2019-08, Vol.35 (4), p.485-495

2019

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Built-in self-test for phase-locked loops

IEEE transactions on instrumentation and measurement, 2005-06, Vol.54 (3), p.996-1002

2005

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IEEE_Xplore

Testing of in-memory-computing memories with 8 T SRAMs

Microelectronics and reliability, 2021-08, Vol.123, p.114215, Article 114215

2021

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Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder

IEEE transactions on computers, 2011-05, Vol.60 (5), p.628-638

2011

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IEEE_Xplore

Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications

IEEE transactions on very large scale integration (VLSI) systems, 2012-04, Vol.20 (4), p.665-672

2012

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IEEE_Xplore

Interlaced switch boxes placement for three-dimensional FPGA architecture design

International journal of circuit theory and applications, 2012-05, Vol.40 (5), p.489-502

2012

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Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays

IEEE transactions on very large scale integration (VLSI) systems, 2010-02, Vol.18 (2), p.319-324

2010

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IEEE_Xplore

Novel Built-In Current-Sensor-Based [Formula Omitted] Testing Scheme for CMOS Integrated Circuits

IEEE transactions on instrumentation and measurement, 2009-07, Vol.58 (7), p.2196

2009

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Testing of In-Memory-Computing 8T SRAMs

2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2019, p.1-4

2019

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Testing of Configurable 8T SRAMs for In-Memory Computing

2020 IEEE 29th Asian Test Symposium (ATS), 2020, p.1-5

2020

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IEEE_Xplore

A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications

Journal of signal processing systems, 2008-09, Vol.52 (3), p.211-229

2008

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Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs

2013 22nd Asian Test Symposium, 2013, p.107-108

2013

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IEEE_Xplore

A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010, p.122-128

2010

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IEEE_Xplore

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM

2013 22nd Asian Test Symposium, 2013, p.123-127

2013

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IEEE_Xplore

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM

Journal of electronic testing, 2016-04, Vol.32 (2), p.111-123

2016

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Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010, p.136-143

2010

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IEEE_Xplore

Low-Power built-in logic block observer realization for BIST applications

2007 7th International Conference on ASIC, 2007, p.994-997

2007

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IEEE_Xplore

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Multiple-Wearable-Sensor-Based Gait Classification and Analysis in Patients with Neurological Disorders

Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA

Machine Learning-Based Detection Method for Wafer Test Induced Defects

Wafer Defect Pattern Labeling and Recognition Using Semi-Supervised Learning

Fault-Aware Dependability Enhancement Techniques for Flash Memories

Surface EMG vs. High-Density EMG: Tradeoff Between Performance and Usability for Head Orientation Prediction in VR Application

Fault-Aware Dependability Enhancement Techniques for Phase Change Memory

Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application

Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM

Built-in self-test for phase-locked loops

Testing of in-memory-computing memories with 8 T SRAMs

Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder

Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications

Interlaced switch boxes placement for three-dimensional FPGA architecture design

Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays

Novel Built-In Current-Sensor-Based [Formula Omitted] Testing Scheme for CMOS Integrated Circuits

Testing of In-Memory-Computing 8T SRAMs

Testing of Configurable 8T SRAMs for In-Memory Computing

A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs

A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM

Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications

Low-Power built-in logic block observer realization for BIST applications

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