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Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.2159-2163

2020

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A fixed point exponential function accelerator for a neuromorphic many-core system

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits

IEEE transactions on biomedical circuits and systems, 2016-02, Vol.10 (1), p.243-254

2016

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Determination of growth hormone releasing peptides (GHRP) and their major metabolites in human urine for doping controls by means of liquid chromatography mass spectrometry

Analytical and bioanalytical chemistry, 2011-08, Vol.401 (2), p.507-516

2011

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A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2013-11, Vol.60 (11), p.741-745

2013

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Hardware Implementation of an OPC UA Server for Industrial Field Devices

IEEE transactions on very large scale integration (VLSI) systems, 2021-11, Vol.29 (11), p.1998-2002

2021

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Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype

Frontiers in neuroscience, 2018-11, Vol.12, p.840-840

2018

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A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2014-11, Vol.61 (11), p.835-839

2014

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A compact on-chip IR-drop measurement system in 28 nm CMOS technology

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1219-1222

2014

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Rapid high resolution genotyping of Francisella tularensis by whole genome sequence comparison of annotated genes ("MLST+")

PloS one, 2015-04, Vol.10 (4), p.e0123298-e0123298

2015

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An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

IEEE journal of solid-state circuits, 2015-03, Vol.50 (3), p.749-762

2015

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A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

IEEE transactions on biomedical circuits and systems, 2022-02, Vol.16 (1), p.94-107

2022

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Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype

IEEE transactions on biomedical circuits and systems, 2019-06, Vol.13 (3), p.579-591

2019

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Hard Real-Time Capable OPC UA Server as Hardware Peripheral for Single Chip IoT Systems

2019 24th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), 2019, p.1631-1634

2019

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Mass spectrometric studies on the in vitro generated metabolites of SIRT1 activating drugs for doping control purposes

Journal of mass spectrometry., 2013-07, Vol.48 (7), p.830-843

2013

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Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

Frontiers in neuroscience, 2015-02, Vol.9, p.10-10

2015

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Power Minimization in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning

IEEE solid-state circuits letters, 2023, Vol.6, p.145-148

2023

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A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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Hardware Acceleration of EEG-Based Emotion Classification Systems: A Comprehensive Survey

IEEE transactions on biomedical circuits and systems, 2021-06, Vol.15 (3), p.412-442

2021

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An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.739-743

2022

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Complementing the characterization of in vivo generated N-glucuronic acid conjugates of stanozolol by collision cross section computation and analysis

Drug testing and analysis, 2015-11, Vol.7 (11-12), p.1050-1056

2015

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Power Minimisation in Neural Recording ∆Σ Modulators by Adaptive Back-Gate Voltage Tuning

IEEE solid-state circuits letters, 2023-04, p.1-1

2023

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A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring

IEEE transactions on very large scale integration (VLSI) systems, 2016-12, Vol.24 (12), p.3548-3552

2016

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A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

Analog integrated circuits and signal processing, 2015-09, Vol.84 (3), p.421-431

2015

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Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

A fixed point exponential function accelerator for a neuromorphic many-core system

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits

Determination of growth hormone releasing peptides (GHRP) and their major metabolites in human urine for doping controls by means of liquid chromatography mass spectrometry

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

Hardware Implementation of an OPC UA Server for Industrial Field Devices

Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology

A compact on-chip IR-drop measurement system in 28 nm CMOS technology

Rapid high resolution genotyping of Francisella tularensis by whole genome sequence comparison of annotated genes ("MLST+")

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype

Hard Real-Time Capable OPC UA Server as Hardware Peripheral for Single Chip IoT Systems

Mass spectrometric studies on the in vitro generated metabolites of SIRT1 activating drugs for doping control purposes

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

Power Minimization in Neural Recording ΔΣ Modulators by Adaptive Back-Gate Voltage Tuning

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology

Hardware Acceleration of EEG-Based Emotion Classification Systems: A Comprehensive Survey

An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology

Complementing the characterization of in vivo generated N-glucuronic acid conjugates of stanozolol by collision cross section computation and analysis

Power Minimisation in Neural Recording ∆Σ Modulators by Adaptive Back-Gate Voltage Tuning

A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration

A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring

A 10 bit 16-to-26 MS/s flexible window SAR ADC for digitally controlled DC–DC converters in 28 nm CMOS

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