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Low Schottky barrier height for silicides on n -type Si (100) by interfacial selenium segregation during silicidation

Applied physics letters, 2008-08, Vol.93 (7), p.072103-072103-3

2008

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Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

IEEE electron device letters, 2007-12, Vol.28 (12), p.1102-1104

2007

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Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

IEEE electron device letters, 2007-08, Vol.28 (8), p.703-705

2007

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Contact Resistance Reduction Technology Using Selenium Segregation for N-MOSFETs With Silicon-Carbon Source/Drain

IEEE transactions on electron devices, 2009-05, Vol.56 (5), p.1128-1134

2009

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Selenium Segregation for Lowering the Contact Resistance in Ultrathin-Body MOSFETs With Fully Metallized Source/Drain

IEEE electron device letters, 2009-10, Vol.30 (10), p.1087-1089

2009

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Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With Silicon-Carbon Source/Drain Stressors

IEEE electron device letters, 2008-08, Vol.29 (8), p.841-844

2008

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Laser Annealing of Amorphous Germanium on Silicon-Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

IEEE electron device letters, 2008-08, Vol.29 (8), p.885-888

2008

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Silicon-Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

IEEE electron device letters, 2008-05, Vol.29 (5), p.460-463

2008

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Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation

IEEE electron device letters, 2008-07, Vol.29 (7), p.756-758

2008

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Strained Silicon Nanowire p-Channel FETs With Diamond-Like Carbon Liner Stressor

IEEE electron device letters, 2010-12, Vol.31 (12), p.1371-1373

2010

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Strained n-Channel Field-Effect Transistors with Channel Proximate Silicon–Carbon Source/Drain Stressors for Performance Enhancement

Journal of the Electrochemical Society, 2010, Vol.157 (12), p.H1088

2010

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Gate-all-around quantum-wire field-effect transistor with Dopant Segregation at Metal-Semiconductor-Metal heterostucture

2009 Symposium on VLSI Technology, 2009, p.92-93

2009

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Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance

2008 Symposium on VLSI Technology, 2008, p.28-29

2008

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Selenium Co-implantation and segregation as a new contact technology for nanoscale SOI N-FETs featuring NiSi:C formed on silicon-carbon (Si:C) source/drain stressors

2008 Symposium on VLSI Technology, 2008, p.168-169

2008

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A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced local melting and recrystallization for P-FET performance enhancement

2008 Symposium on VLSI Technology, 2008, p.26-27

2008

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A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2008, p.36-37

2008

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Contact Resistance Reduction Technology Using Selenium Segregation for N-MOSFETs With SiliconaCarbon Source/Drain

IEEE transactions on electron devices, 2009-01, Vol.56 (5)

2009

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Enhanced performance in strained n-FET with double-recessed Si:C source/drain and lattice-mismatched SiGe strain-transfer structure (STS)

2007 International Semiconductor Device Research Symposium, 2007, p.1-2

2007

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Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With SiliconaCarbon Source/Drain Stressors

IEEE electron device letters, 2008-01, Vol.29 (8)

2008

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Source/drain-extension-last process for incorporating in situ doped lattice-mismatched extension stressor for enhanced performance in SOI N-FET

2007 International Semiconductor Device Research Symposium, 2007, p.1-2

2007

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Laser Annealing of Amorphous Germanium on SiliconaGermanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

IEEE electron device letters, 2008-01, Vol.29 (8)

2008

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Silicon-Carbon Stressors With High Substitutional Carbon Concentration and @@iIn Situ@ Doping Formed in Source/Drain Extensions of n-Channel Transistors

IEEE electron device letters, 2008-05, Vol.29 (5), p.460-463

2008

Volltextzugriff (PDF)

SiliconaCarbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

IEEE electron device letters, 2008-01, Vol.29 (5)

2008

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Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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Low Schottky barrier height for silicides on n -type Si (100) by interfacial selenium segregation during silicidation

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

Sub-0.1-eV Effective Schottky-Barrier Height for NiSi on n-Type Si (100) Using Antimony Segregation

Contact Resistance Reduction Technology Using Selenium Segregation for N-MOSFETs With Silicon-Carbon Source/Drain

Selenium Segregation for Lowering the Contact Resistance in Ultrathin-Body MOSFETs With Fully Metallized Source/Drain

Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With Silicon-Carbon Source/Drain Stressors

Laser Annealing of Amorphous Germanium on Silicon-Germanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

Silicon-Carbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

Source and Drain Series Resistance Reduction for N-Channel Transistors Using Solid Antimony (Sb) Segregation (SSbS) During Silicidation

Strained Silicon Nanowire p-Channel FETs With Diamond-Like Carbon Liner Stressor

Strained n-Channel Field-Effect Transistors with Channel Proximate Silicon–Carbon Source/Drain Stressors for Performance Enhancement

Gate-all-around quantum-wire field-effect transistor with Dopant Segregation at Metal-Semiconductor-Metal heterostucture

Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance

Selenium Co-implantation and segregation as a new contact technology for nanoscale SOI N-FETs featuring NiSi:C formed on silicon-carbon (Si:C) source/drain stressors

A new source/drain germanium-enrichment process comprising Ge deposition and laser-induced local melting and recrystallization for P-FET performance enhancement

A New Salicidation Process with Solid Antimony (Sb) Segregation (SSbS) for Achieving Sub-0.1 eV Effective Schottky Barrier Height and Parasitic Series Resistance Reduction in N-Channel Transistors

Contact Resistance Reduction Technology Using Selenium Segregation for N-MOSFETs With SiliconaCarbon Source/Drain

Enhanced performance in strained n-FET with double-recessed Si:C source/drain and lattice-mismatched SiGe strain-transfer structure (STS)

Novel Nickel Silicide Contact Technology Using Selenium Segregation for SOI N-FETs With SiliconaCarbon Source/Drain Stressors

Source/drain-extension-last process for incorporating in situ doped lattice-mismatched extension stressor for enhanced performance in SOI N-FET

Laser Annealing of Amorphous Germanium on SiliconaGermanium Source/Drain for Strain and Performance Enhancement in pMOSFETs

Silicon-Carbon Stressors With High Substitutional Carbon Concentration and @@iIn Situ@ Doping Formed in Source/Drain Extensions of n-Channel Transistors

SiliconaCarbon Stressors With High Substitutional Carbon Concentration and In Situ Doping Formed in Source/Drain Extensions of n-Channel Transistors

Novel Nickel-Alloy Silicides for Source/Drain Contact Resistance Reduction in N-Channel Multiple-Gate Transistors with Sub-35nm Gate Length

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