UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 91

Sortiert nach

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

IEEE transactions on electron devices, 2019-05, Vol.66 (5), p.2075-2080

2019

Volltextzugriff (PDF)

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

IEEE transactions on electron devices, 2018-10, Vol.65 (10), p.4238-4244

2018

Volltextzugriff (PDF)

Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs

IEEE transactions on electron devices, 2016-10, Vol.63 (10), p.4046-4052

2016

Volltextzugriff (PDF)

Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

IEEE transactions on electron devices, 2020-05, Vol.67 (5), p.2208-2212

2020

Volltextzugriff (PDF)

Series Resistance Reduction With Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET

IEEE transactions on electron devices, 2018-08, Vol.65 (8), p.3548-3554

2018

Volltextzugriff (PDF)

OFF-State Leakage and Performance Variations Associated With Germanium Preamorphization Implant in Silicon-Germanium Channel pFET

IEEE transactions on electron devices, 2018-09, Vol.65 (9), p.3654-3661

2018

Volltextzugriff (PDF)

Toward Microwave S- and X-Parameter Approaches for the Characterization of Ferroelectrics for Applications in FeFETs and NCFETs

IEEE transactions on electron devices, 2019-04, Vol.66 (4), p.2028-2035

2019

Volltextzugriff (PDF)

Vertical Slit FET at 7-nm Node and Beyond

IEEE transactions on electron devices, 2016-08, Vol.63 (8), p.3327-3334

2016

Volltextzugriff (PDF)

Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements

IEEE electron device letters, 2013-09, Vol.34 (9), p.1100-1102

2013

Volltextzugriff (PDF)

Impact of Short-Wavelength and Long-Wavelength Line-Edge Roughness on the Variability of Ultrascaled FinFETs

IEEE transactions on electron devices, 2017-03, Vol.64 (3), p.1231-1238

2017

Volltextzugriff (PDF)

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

IEEE transactions on electron devices, 2011-02, Vol.58 (2), p.335-342

2011

Volltextzugriff (PDF)

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

IEEE electron device letters, 2008-07, Vol.29 (7), p.802-804

2008

Volltextzugriff (PDF)

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

Japanese Journal of Applied Physics, 2016-04, Vol.55 (4S), p.4

2016

Volltextzugriff (PDF)

Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond

IEEE journal of the Electron Devices Society, 2018-01, Vol.6, p.551-556

2018

Volltextzugriff (PDF)

Comment on "Channel Length and Threshold Voltage Dependence of a Transistor Mismatch in a 32-nm HKMG Technology"

IEEE transactions on electron devices, 2011-04, Vol.58 (4), p.1255-1256

2011

Volltextzugriff (PDF)

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

IEEE journal of the Electron Devices Society, 2016-09, Vol.4 (5), p.266-272

2016

Volltextzugriff (PDF)

Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets

Joule, 2018-01, Vol.2 (1), p.1-4

Hook, Terence B.

2018

Volltextzugriff (PDF)

Channel Length and Threshold Voltage Dependence of Transistor Mismatch in a 32-nm HKMG Technology

IEEE transactions on electron devices, 2010-10, Vol.57 (10), p.2440-2447

2010

Volltextzugriff (PDF)

Anomalous Dependence of Threshold Voltage Mismatch of Short-Channel Transistors

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2805-2807

2011

Volltextzugriff (PDF)

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

IEEE transactions on electron devices, 2018-03, Vol.65 (3), p.1246-1252

2018

Volltextzugriff (PDF)

Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs

IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5274-5278

2017

Volltextzugriff (PDF)

Noise margin and leakage in ultra-low leakage SRAM cell design

IEEE transactions on electron devices, 2002-08, Vol.49 (8), p.1499-1501

2002

Volltextzugriff (PDF)

High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step

IEEE transactions on electron devices, 2002-09, Vol.49 (9), p.1623-1627

2002

Volltextzugriff (PDF)

Scalability of planar FDSOI and FinFETs and What's in store for the future beyond that?

2015 45th European Solid State Device Research Conference (ESSDERC), 2015, p.160-163

2015

Volltextzugriff (PDF)

Channel Material Dependence of Wave Function Deformation Scattering in Ultrascaled FinFETs

IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5107-5113

2017

Volltextzugriff (PDF)

1 – 25 von 91

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(63)
Mit Volltextzugriff
(81)

Publikationsform

1 weiteren anzeigen...

Weniger anzeigen...

Sprache

Englisch
(91)
Japanisch
(14)

Erscheinungsjahr

n.n

Thema

Science & Technology
(58)
Technology
(49)
Engineering
(48)
Engineering, Electrical & Electronic
(48)
Physical Sciences
(42)
Physics
(41)
Physics, Applied
(39)
Logic Gates
(24)
Silicon
(19)
Threshold Voltage
(19)
Applied Sciences
(17)
Exact Sciences And Technology
(17)
Electronics
(16)
Finfets
(16)
Semiconductor Electronics. Microelectronics. Optoelectronics. Solid State Devices
(16)
Doping
(14)
Transistors
(13)
Humans
(11)
Cmos
(10)
Cmos Technology
(10)

15 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs

Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

Series Resistance Reduction With Linearity Assessment for Vertically Stacked Junctionless Accumulation Mode Nanowire FET

OFF-State Leakage and Performance Variations Associated With Germanium Preamorphization Implant in Silicon-Germanium Channel pFET

Toward Microwave S- and X-Parameter Approaches for the Characterization of Ferroelectrics for Applications in FeFETs and NCFETs

Vertical Slit FET at 7-nm Node and Beyond

Efficient and Accurate Schematic Transistor Model of FinFET Parasitic Elements

Impact of Short-Wavelength and Long-Wavelength Line-Edge Roughness on the Variability of Ultrascaled FinFETs

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond

Comment on "Channel Length and Threshold Voltage Dependence of a Transistor Mismatch in a 32-nm HKMG Technology"

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets

Channel Length and Threshold Voltage Dependence of Transistor Mismatch in a 32-nm HKMG Technology

Anomalous Dependence of Threshold Voltage Mismatch of Short-Channel Transistors

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

Analytical Modeling of Parasitic Capacitance in Inserted-Oxide FinFETs

Noise margin and leakage in ultra-low leakage SRAM cell design

High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step

Scalability of planar FDSOI and FinFETs and What's in store for the future beyond that?

Channel Material Dependence of Wave Function Deformation Scattering in Ultrascaled FinFETs

Suchergebnisse filtern