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Evaluation of 10-nm Bulk FinFET RF Performance-Conventional Versus NC-FinFET

IEEE electron device letters, 2018-08, Vol.39 (8), p.1246-1249

2018

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Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates

Microelectronic engineering, 2005-06, Vol.80, p.126-129

2005

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Lateral ion implant straggle and mask proximity effect

IEEE transactions on electron devices, 2003-09, Vol.50 (9), p.1946-1951

2003

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Transistor mismatch in 32 nm high-k metal-gate process

Electronics letters, 2010-05, Vol.46 (10), p.708-709

2010

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Spurious source/drain underlap of large junction area NFET's

IEEE transactions on semiconductor manufacturing, 1999-08, Vol.12 (3), p.381-382

Hook, T.B.

1999

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The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology

IEEE transactions on electron devices, 2001-07, Vol.48 (7), p.1346-1353

2001

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Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

IBM journal of research and development, 1999-05, Vol.43 (3), p.393-406

1999

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Correlation between fixed positive charge and hot-electron immunity for nitridized oxides

IEEE electron device letters, 1997-10, Vol.18 (10), p.471-473

1997

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Polyimide-related design considerations in a bipolar technology

IEEE transactions on electron devices, 1990-07, Vol.37 (7), p.1714-1718

Hook, T.B.

1990

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Titanium silicide/silicon nonohmic contact resistance for NFET's, PFET's, diffused resistors, and NPN's in a BiCMOS technology

IEEE transactions on electron devices, 1995-04, Vol.42 (4), p.697-703

1995

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Ultralow-power SRAM technology

IBM journal of research and development, 2003-09, Vol.47 (5.6), p.553-566

2003

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Noise margin and leakage in ultra-low leakage SRAM cell design

IEEE transactions on electron devices, 2002-08, Vol.49 (8), p.1499-1501

2002

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Automatic extraction of circuit models from layout artwork for a BiCMOS technology

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-06, Vol.11 (6), p.732-738

Hook, T.B.

1992

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High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step

IEEE transactions on electron devices, 2002-09, Vol.49 (9), p.1623-1627

2002

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Fully depleted devices for designers: FDSOI and FinFETs

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-7

Hook, T. B.

2012

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Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

IEEE transactions on electron devices, 2011-02, Vol.58 (2), p.335-342

2011

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Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

IEEE electron device letters, 2008-07, Vol.29 (7), p.802-804

2008

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Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation

Microelectronics and reliability, 2001-05, Vol.41 (5), p.751-765

2001

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The dependence of channel length on channel width in narrow-channel CMOS devices for 0.35-0.13 μm technologies

IEEE electron device letters, 2000-02, Vol.21 (2), p.85-87

2000

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Process stability of deuterium-annealed MOSFET's

IEEE electron device letters, 1999-01, Vol.20 (1), p.48-50

1999

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The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

IEEE transactions on electron devices, 1999-04, Vol.46 (4), p.747-753

1999

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Nonrandom Device Mismatch Considerations in Nanoscale SRAM

IEEE transactions on very large scale integration (VLSI) systems, 2012-07, Vol.20 (7), p.1211-1220

2012

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Anomalous Dependence of Threshold Voltage Mismatch of Short-Channel Transistors

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2805-2807

2011

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Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

2013 IEEE International Electron Devices Meeting, 2013, p.13.5.1-13.5.4

2013

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Channel length dependence of random telegraph signal in sub-micron MOSFET's

IEEE electron device letters, 1994-12, Vol.15 (12), p.504-506

1994

Volltextzugriff (PDF)

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Evaluation of 10-nm Bulk FinFET RF Performance-Conventional Versus NC-FinFET

Interface state generation in pFETs with ultra-thin oxide and oxynitride on (100) and (110) Si substrates

Lateral ion implant straggle and mask proximity effect

Transistor mismatch in 32 nm high-k metal-gate process

Spurious source/drain underlap of large junction area NFET's

The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

Correlation between fixed positive charge and hot-electron immunity for nitridized oxides

Polyimide-related design considerations in a bipolar technology

Titanium silicide/silicon nonohmic contact resistance for NFET's, PFET's, diffused resistors, and NPN's in a BiCMOS technology

Ultralow-power SRAM technology

Noise margin and leakage in ultra-low leakage SRAM cell design

Automatic extraction of circuit models from layout artwork for a BiCMOS technology

High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step

Fully depleted devices for designers: FDSOI and FinFETs

Transistor Mismatch Properties in Deep-Submicrometer CMOS Technologies

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond

Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation

The dependence of channel length on channel width in narrow-channel CMOS devices for 0.35-0.13 μm technologies

Process stability of deuterium-annealed MOSFET's

The combined effects of deuterium anneals and deuterated barrier-nitride processing on hot-electron degradation in MOSFET's

Nonrandom Device Mismatch Considerations in Nanoscale SRAM

Anomalous Dependence of Threshold Voltage Mismatch of Short-Channel Transistors

Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

Channel length dependence of random telegraph signal in sub-micron MOSFET's

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