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Advanced DC-SF Cell Technology for 3-D NAND Flash

IEEE transactions on electron devices, 2013-04, Vol.60 (4), p.1327-1333

2013

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Memory technology trend and future challenges

2010 International Electron Devices Meeting, 2010, p.12.4.1-12.4.4

Sungjoo Hong

2010

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Novel Negative $Vt$ Shift Phenomenon of Program-Inhibit Cell in $\hbox{2}X{-}\hbox{3}X\hbox{-}\hbox{nm}$ Self-Aligned STI nand Flash Memory

IEEE transactions on electron devices, 2012-11, Vol.59 (11), p.2950-2955

2012

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Transient 3-D TCAD simulation of multiple snapback event in mixed-mode test for mutual relation between protection devices

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, p.467-470

2015

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Novel negative Vt shift program disturb phenomena in 2X∼3X nm NAND flash memory cells

2011 International Reliability Physics Symposium, 2011, p.6B.2.1-6B.2.4

2011

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A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

2012 Symposium on VLSI Technology (VLSIT), 2012, p.19-20

2012

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Novel Negative Vt Shift Phenomenon of Program-Inhibit Cell in 2X-3X-nm Self-Aligned STI NAND Flash Memory

IEEE transactions on electron devices, 2012-11, Vol.59 (11), p.2950-2955

2012

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Novel Negative [Formula Omitted] Shift Phenomenon of Program-Inhibit Cell in [Formula Omitted] Self-Aligned STI nand Flash Memory

IEEE transactions on electron devices, 2012-11, Vol.59 (11), p.2950

2012

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Novel Negative Vt Shift Phenomenon of Program-Inhibit Cell in \hboxX\hboxX\hbox\hbox Self-Aligned STI nand Flash Memory

IEEE transactions on electron devices, 2012-11, Vol.59 (11), p.2950-2955

2012

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Novel Negative Vt Shift Phenomenon of Program-Inhibit Cell in hbox 2 X - hbox 3 X hbox - hbox nm Self-Aligned STI nand Flash Memory

IEEE transactions on electron devices, 2012-11, Vol.59 (11), p.2950-2955

2012

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Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.21.6.1-21.6.4

2017

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A novel three-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell

Solid-state electronics, 2013-01, Vol.79, p.166-171

2013

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TCAD Simulation of Data Retention Characteristics of Charge Trap Device for 3-D NAND Flash Memory

2015 IEEE International Memory Workshop (IMW), 2015, p.1-4

2015

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An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014, p.1-2

2014

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A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

2011 International Electron Devices Meeting, 2011, p.9.1.1-9.1.4

2011

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Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory

2013 5th IEEE International Memory Workshop, 2013, p.147-150

2013

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New Read Scheme of Variable Vpass-Read for Dual Control Gate with Surrounding Floating Gate (DC-SF) NAND Flash Cell

2011 3rd IEEE International Memory Workshop (IMW), 2011, p.1-4

2011

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Advanced Hot-Carrier Injection Programming Scheme for Sub 20nm NAND Flash Cell and beyond

2012 4th IEEE International Memory Workshop, 2012, p.1-4

2012

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25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.432-433

2014

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25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.434-435

2014

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Analysis of DRAM EMI dependence on data pattern and power delivery design using a near-field EMI scanner

2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008, p.271-274

2008

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Semiconductor memory scaling and beyond

2012 IEEE Asian Solid State Circuits Conference (A-SSCC), 2012, p.5-8

SungJoo Hong

2012

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Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application

2010 International Electron Devices Meeting, 2010, p.29.7.1-29.7.4

2010

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2D–Organic Hybrid Heterostructures for Optoelectronic Applications

Advanced materials (Weinheim), 2019-08, Vol.31 (34), p.e1803831-n/a

2019

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A scalable processing-in-memory accelerator for parallel graph processing

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.105-117

2015

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Advanced DC-SF Cell Technology for 3-D NAND Flash

Memory technology trend and future challenges

Novel Negative $Vt$ Shift Phenomenon of Program-Inhibit Cell in $\hbox{2}X{-}\hbox{3}X\hbox{-}\hbox{nm}$ Self-Aligned STI nand Flash Memory

Transient 3-D TCAD simulation of multiple snapback event in mixed-mode test for mutual relation between protection devices

Novel negative Vt shift program disturb phenomena in 2X∼3X nm NAND flash memory cells

A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory

Novel Negative Vt Shift Phenomenon of Program-Inhibit Cell in 2X-3X-nm Self-Aligned STI NAND Flash Memory

Novel Negative [Formula Omitted] Shift Phenomenon of Program-Inhibit Cell in [Formula Omitted] Self-Aligned STI nand Flash Memory

Novel Negative Vt Shift Phenomenon of Program-Inhibit Cell in \hboxX\hboxX\hbox\hbox Self-Aligned STI nand Flash Memory

Novel Negative Vt Shift Phenomenon of Program-Inhibit Cell in hbox 2 X - hbox 3 X hbox - hbox nm Self-Aligned STI nand Flash Memory

Overcoming the reliability limitation in the ultimately scaled DRAM using silicon migration technique by hydrogen annealing

A novel three-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell

TCAD Simulation of Data Retention Characteristics of Charge Trap Device for 3-D NAND Flash Memory

An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM

A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

Modeling and optimization of the chip level program disturbance of 3D NAND Flash memory

New Read Scheme of Variable Vpass-Read for Dual Control Gate with Surrounding Floating Gate (DC-SF) NAND Flash Cell

Advanced Hot-Carrier Injection Programming Scheme for Sub 20nm NAND Flash Cell and beyond

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

Analysis of DRAM EMI dependence on data pattern and power delivery design using a near-field EMI scanner

Semiconductor memory scaling and beyond

Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application

2D–Organic Hybrid Heterostructures for Optoelectronic Applications

A scalable processing-in-memory accelerator for parallel graph processing

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