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Application Specific Routing Algorithms for Networks on Chip

IEEE transactions on parallel and distributed systems, 2009-03, Vol.20 (3), p.316-330

2009

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Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs

IEEE transactions on very large scale integration (VLSI) systems, 2009-03, Vol.17 (3), p.356-369

2009

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Modelling and Evaluation of a Network on Chip Architecture Using SDL

11th International SDL Forum Stuttgart, Germany, July 1-4, 2003, 2003, Vol.2708, p.166-182

2003

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An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010, p.37-44

2010

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A methodology for design of application specific deadlock-free routing algorithms for NoC systems

International Conference on Hardware Software Codesign: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis; 22-25 Oct. 2006, 2006, p.142-147

2006

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An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs

2011 IEEE 11th International Conference on Computer and Information Technology, 2011, p.59-66

2011

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HiRA: A methodology for deadlock free routing in hierarchical networks on chip

2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009, p.2-11

2009

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Design issues and performance evaluation of mesh NoC with regions

2005 NORCHIP, 2005, p.40-43

2005

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Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 2008, p.97-106

2008

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Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions

9th EUROMICRO Conference on Digital System Design (DSD'06), 2006, p.696-703

2006

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Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms

2007 IEEE International Parallel and Distributed Processing Symposium, 2007, p.1-8

2007

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A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms

Euro-Par 2010 Parallel Processing Workshops, 2011, p.153-161

2011

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Application Specific Routing Algorithms for Networks on Chip

Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs

Modelling and Evaluation of a Network on Chip Architecture Using SDL

An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip

A methodology for design of application specific deadlock-free routing algorithms for NoC systems

An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs

HiRA: A methodology for deadlock free routing in hierarchical networks on chip

Design issues and performance evaluation of mesh NoC with regions

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions

Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms

A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms

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