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Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4368-4373

2013

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Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

IEEE transactions on nuclear science, 2018-01, Vol.65 (1), p.362-368

2018

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On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2748-2755

2012

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Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.2613-2619

2015

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Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4399-4404

2013

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Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process

IEEE transactions on nuclear science, 2017-01, Vol.64 (1), p.477-482

2017

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Impact of Process Variations and Charge Sharing on the Single-Event-Upset Response of Flip-Flops

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.2658-2663

2011

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A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

IEEE transactions on nuclear science, 2006-12, Vol.53 (6), p.3432-3438

2006

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Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

IEEE transactions on nuclear science, 2013-12, Vol.60 (6), p.4498-4504

2013

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Impact of Process Variations on SRAM Single Event Upsets

IEEE transactions on nuclear science, 2011-06, Vol.58 (3), p.834-839

2011

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Demonstration of a Differential Layout Solution for Improved ASET Tolerance in CMOS A/MS Circuits

IEEE transactions on nuclear science, 2010-12, Vol.57 (6), p.3615-3619

2010

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Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2867-2871

2012

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RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation

IEEE transactions on nuclear science, 2011-12, Vol.58 (6), p.3060-3066

2011

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Single-Event Analysis and Hardening of Mixed-Signal Circuit Interfaces in High-Speed Communications Devices

IEEE transactions on nuclear science, 2012-08, Vol.59 (4), p.1027-1033

2012

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Digital Control for Radiation-Hardened Switching Converters in Space

IEEE transactions on aerospace and electronic systems, 2010-04, Vol.46 (2), p.761-770

2010

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Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

IEEE transactions on nuclear science, 2020-06, Vol.67 (6), p.1144-1151

2020

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Single-Event Transient Error Characterization of a Radiation-Hardened by Design 90 nm SerDes Transmitter Driver

IEEE transactions on nuclear science, 2009-12, Vol.56 (6), p.3463-3468

2009

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Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology

IEEE transactions on nuclear science, 2018-01, Vol.65 (1), p.413-417

2018

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Dual-Interlocked Logic for Single-Event Transient Mitigation

IEEE transactions on nuclear science, 2018-08, Vol.65 (8), p.1872-1878

2018

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Modeling Total-Dose Effects for a Low-Dropout Voltage Regulator

IEEE transactions on nuclear science, 2006-12, Vol.53 (6), p.3223-3231

2006

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Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2561-2567

2007

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Single-Event Upset Characterization of Common First- and Second-Order All-Digital Phase-Locked Loops

IEEE transactions on nuclear science, 2017-08, Vol.64 (8), p.2144-2151

2017

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Total dose effects in a linear Voltage regulator

IEEE transactions on nuclear science, 2004-12, Vol.51 (6), p.3816-3821

2004

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Time-Domain Modeling of All-Digital PLLs to Single-Event Upset Perturbations

IEEE transactions on nuclear science, 2018-01, Vol.65 (1), p.311-317

2018

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Radiation Hardening of Voltage References Using Chopper Stabilization

IEEE transactions on nuclear science, 2015-12, Vol.62 (6), p.3064-3071

2015

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Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections

Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process

Impact of Process Variations and Charge Sharing on the Single-Event-Upset Response of Flip-Flops

A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

Impact of Process Variations on SRAM Single Event Upsets

Demonstration of a Differential Layout Solution for Improved ASET Tolerance in CMOS A/MS Circuits

Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation

Single-Event Analysis and Hardening of Mixed-Signal Circuit Interfaces in High-Speed Communications Devices

Digital Control for Radiation-Hardened Switching Converters in Space

Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

Single-Event Transient Error Characterization of a Radiation-Hardened by Design 90 nm SerDes Transmitter Driver

Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology

Dual-Interlocked Logic for Single-Event Transient Mitigation

Modeling Total-Dose Effects for a Low-Dropout Voltage Regulator

Modeling and Mitigating Single-Event Transients in Voltage-Controlled Oscillators

Single-Event Upset Characterization of Common First- and Second-Order All-Digital Phase-Locked Loops

Total dose effects in a linear Voltage regulator

Time-Domain Modeling of All-Digital PLLs to Single-Event Upset Perturbations

Radiation Hardening of Voltage References Using Chopper Stabilization

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