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The TaPaSCo Open-Source Toolflow: for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems

Journal of signal processing systems, 2021-05, Vol.93 (5), p.545-563

2021

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DISCO: Distributed Inference with Sparse Communications

2024 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV), 2024, p.2421-2429

2024

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Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases

2021 International Conference on Field-Programmable Technology (ICFPT), 2021, p.1-9

2021

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Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design

2020 IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers (ROSS), 2020, p.22-30

2020

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An Improved Framework for and Case Studies in FPGA-Based Application Acceleration - Computer Vision, In-Network Processing and Spiking Neural Networks

Hofmann, Jaco

2020

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A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors

2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2019, p.1-8

2019

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The TaPaSCo Open-Source Toolflow

Journal of signal processing systems, 2021-01, Vol.93 (5), p.545-563

2021

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High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud

2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), 2019, p.26-33

2019

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A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation

IEEE transactions on biomedical circuits and systems, 2018-04, Vol.12 (2), p.326-337

2018

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Consensus for Non-volatile Main Memory

2018 IEEE 26th International Conference on Network Protocols (ICNP), 2018, p.406-411

2018

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Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases

Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021, Vol.12700, p.18-32

2021

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The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems

Applied Reconfigurable Computing, 2019, Vol.11444, p.214-229

2019

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Multi-Chip Dataflow Architecture for Massive Scale Biophyscially Accurate Neuron Simulation

Real-Time Multi-Chip Neural Network for Cognitive Systems, 2019, p.23-47

1, 2019

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Multi-Chip Dataflow Architecture for Massive Scale Biophysically Accurate Neuron Simulation

Real-Time Multi-Chip Neural Network for Cognitive Systems, 2018

2018

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Online Reprogrammable Multi Tenant Switches

Proceedings of the 1st ACM CoNEXT Workshop on Emerging in-Network Computing Paradigms, 2019, p.1-8

2019

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Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation

2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016, Vol.2016, p.5829-5832

2016

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A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching

2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), 2016, p.845-853

2016

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A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2016, p.1-8

2016

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Synthesis of interleaved multithreaded accelerators from OpenMP loops

2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2017, p.1-7

2017

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The TaPaSCo Open-Source Toolflow: for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems

DISCO: Distributed Inference with Sparse Communications

Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases

Improving Job Launch Rates in the TaPaSCo FPGA Middleware by Hardware/Software-Co-Design

An Improved Framework for and Case Studies in FPGA-Based Application Acceleration - Computer Vision, In-Network Processing and Spiking Neural Networks

A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors

The TaPaSCo Open-Source Toolflow

High-Throughput Multi-Threaded Sum-Product Network Inference in the Reconfigurable Cloud

A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation

Consensus for Non-volatile Main Memory

Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases

The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems

Multi-Chip Dataflow Architecture for Massive Scale Biophyscially Accurate Neuron Simulation

Multi-Chip Dataflow Architecture for Massive Scale Biophysically Accurate Neuron Simulation

Online Reprogrammable Multi Tenant Switches

Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation

A Scalable High-Performance Hardware Architecture for Real-Time Stereo Vision by Semi-Global Matching

A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications

Synthesis of interleaved multithreaded accelerators from OpenMP loops

Discovery of WRN inhibitor HRO761 with synthetic lethality in MSI cancers

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