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Kann die Mikroelektronik nach 2010 noch wachsen?

Elektrotechnik und Informationstechnik, 2001-10, Vol.118 (10), p.495-501

Höfflinger, B.

2001

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Chips 2020 Vol. 2: New Vistas in Nanoelectronics

1st ed. 2016, 2015

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Dry etch improvements in the SOI wafer flow process for IPL stencil mask fabrication

Microelectronic engineering, 2000-06, Vol.53 (1), p.609-612

2000

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SOI wafer flow process for stencil mask fabrication

Microelectronic engineering, 1999, Vol.46 (1), p.473-476

1999

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Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED)

Microelectronics and reliability, 1998-12, Vol.38 (12), p.1881-1891

1998

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Silicon fusion bonding and its characterization

Journal of micromechanics and microengineering, 1992-09, Vol.2 (3), p.113-116

1992

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Realisation of irregular quarter-micron patterns in thick resists using an advanced e-beam sensitive TSI process

Microelectronic engineering, 1996-01, Vol.30 (1-4), p.301-304

1996

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Parallel digital neural hardware for controller design

Mathematics and computers in simulation, 1996, Vol.41 (1), p.149-160

1996

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Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth

IEEE transactions on electron devices, 1990-06, Vol.37 (6), p.1452-1461

1990

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A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a 1-micrometer silicon-film-on-insulator-on-silicon

IEEE transactions on electron devices, 1991-07, Vol.38 (7), p.1655-1659

1991

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Economic production of submicron ASICs with laser beam direct write lithography

Microelectronic engineering, 1997-02, Vol.35 (1-4), p.509-512

1997

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Static and dynamic behaviour of power devices in silicon-direct-bonded substrates

Materials science & engineering. B, Solid-state materials for advanced technology, 1995, Vol.29 (1), p.13-17

1995

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Multiconcens: An exposure method for submicron contact-hole layers, using variable-shape electron-beam direct-write and single-layer resist

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 1992, Vol.10 (6), p.2789-2793

1992

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A one-dimensional analytical model for the dual-gate-controlled thin-film SOI MOSFET

IEEE electron device letters, 1991-09, Vol.12 (9), p.489-491

1991

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High-quality stacked CMOS inverter

IEEE electron device letters, 1990-01, Vol.11 (1), p.9-11

1990

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Silicon‐on‐Insulator Films Obtained by Etchback of Bonded Wafers

Journal of the Electrochemical Society, 1989-11, Vol.136 (11), p.3547-3548

1989

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High-quality dual-gate PMOS devices in local overgrowth (LOG)

Electronics letters, 1989-07, Vol.25 (15), p.1009-1011

1989

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First MOS transistors on insulator by silicon saturated liquid solution epitaxy

IEEE electron device letters, 1992-05, Vol.13 (5), p.294-296

1992

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MOS transistors with epitaxial Si, laterally grown over SiO2 by liquid phase epitaxy

Applied Physics A Solids and Surfaces, 1992-01, Vol.54 (1), p.103-105

1992

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Stacked CMOS Technology by Local Overgrowth (LOG)

ESSDERC '89: 19th European Solid State Device Research Conference, 1989, p.877-880

1989

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Ein vorschlag zur verstärkung von plasmawellen in festkörpern mit massenanisotropie

Solid-state electronics, 1965-12, Vol.8 (12), p.907-912

Höfflinger, B.

1965

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Lithography-independent nanometer silicon MOSFETs on insulator

IEEE transactions on electron devices, 1996-10, Vol.43 (10), p.1626-1632

1996

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Optimisation of depletion-mode transistors for an m.o.s. p-channel technology

Electronics letters, 1973-11, Vol.9 (23), p.555

1973

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A Smart Power Process in "Direct-Bondedd'' Silicon on Insulator with 150 V VDMOS, CMOS and Bipolar Transistors

ESSDERC '92: 22nd European Solid State Device Research conference, 1992, p.153-156

1992

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Comparative evaluation of chemically amplified resists for electron-beeam top surface imaging use

Journal of vacuum science & technology. B, Microelectronics and nanometer structures processing, measurement and phenomena, 1994-11, Vol.12 (6), p.3925-3929

1994

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Kann die Mikroelektronik nach 2010 noch wachsen?

Chips 2020 Vol. 2: New Vistas in Nanoelectronics

Dry etch improvements in the SOI wafer flow process for IPL stencil mask fabrication

SOI wafer flow process for stencil mask fabrication

Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED)

Silicon fusion bonding and its characterization

Realisation of irregular quarter-micron patterns in thick resists using an advanced e-beam sensitive TSI process

Parallel digital neural hardware for controller design

Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth

A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a 1-micrometer silicon-film-on-insulator-on-silicon

Economic production of submicron ASICs with laser beam direct write lithography

Static and dynamic behaviour of power devices in silicon-direct-bonded substrates

Multiconcens: An exposure method for submicron contact-hole layers, using variable-shape electron-beam direct-write and single-layer resist

A one-dimensional analytical model for the dual-gate-controlled thin-film SOI MOSFET

High-quality stacked CMOS inverter

Silicon‐on‐Insulator Films Obtained by Etchback of Bonded Wafers

High-quality dual-gate PMOS devices in local overgrowth (LOG)

First MOS transistors on insulator by silicon saturated liquid solution epitaxy

MOS transistors with epitaxial Si, laterally grown over SiO2 by liquid phase epitaxy

Stacked CMOS Technology by Local Overgrowth (LOG)

Ein vorschlag zur verstärkung von plasmawellen in festkörpern mit massenanisotropie

Lithography-independent nanometer silicon MOSFETs on insulator

Optimisation of depletion-mode transistors for an m.o.s. p-channel technology

A Smart Power Process in "Direct-Bondedd'' Silicon on Insulator with 150 V VDMOS, CMOS and Bipolar Transistors

Comparative evaluation of chemically amplified resists for electron-beeam top surface imaging use

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