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A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor

IEEE transactions on information forensics and security, 2019-04, Vol.14 (4), p.1023-1036

2019

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A Secure Data-Toggling SRAM for Confidential Data Protection

IEEE transactions on circuits and systems. I, Regular papers, 2019-11, Vol.66 (11), p.4186-4199

2019

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Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.402-415

2017

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A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection

IEEE transactions on circuits and systems. II, Express briefs, 2021-06, Vol.68 (6), p.2122-2126

2021

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Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design

IEEE transactions on very large scale integration (VLSI) systems, 2018-01, Vol.26 (1), p.196-200

2018

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Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

IEEE journal on emerging and selected topics in circuits and systems, 2021-06, Vol.11 (2), p.343-356

2021

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Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer

IET circuits, devices & systems, 2015-07, Vol.9 (4), p.309-318

2015

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DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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Synthesis of asynchronous QDI circuits using synchronous coding specifications

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.153-156

2014

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Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.353-356

2013

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Normalized Differential Power Analysis - for Ghost Peaks Mitigation

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.3022-3025

2013

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Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.1936-1939

2011

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High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.1913-1916

2015

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Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.850-853

2016

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Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells

2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2019, p.1-7

2019

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Counteracting differential power analysis: Hiding encrypted data from circuit cells

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015, p.297-300

2015

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Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.492-495

2012

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Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM

2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, p.698-701

2016

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A comparative study on asynchronous Quasi-Delay-Insensitive templates

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.1819-1822

2012

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Interceptive side channel attack on AES-128 wireless communications for IoT applications

2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016, p.650-653

2016

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Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014, p.5-8

2014

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High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications

2020 International SoC Design Conference (ISOCC), 2020, p.173-174

2020

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A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation

2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 2018, p.1-5

2018

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High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, p.161-164

2020

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A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor

A Secure Data-Toggling SRAM for Confidential Data Protection

Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template

A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection

Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation

Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer

DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer

Synthesis of asynchronous QDI circuits using synchronous coding specifications

Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU

Normalized Differential Power Analysis - for Ghost Peaks Mitigation

A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic

Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation

High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)

Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications

Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells

Counteracting differential power analysis: Hiding encrypted data from circuit cells

Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic

Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM

A comparative study on asynchronous Quasi-Delay-Insensitive templates

Interceptive side channel attack on AES-128 wireless communications for IoT applications

Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips

High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications

A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation

High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC

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