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A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs

Microelectronic engineering, 2008-05, Vol.85 (5-6), p.996-999

2008

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Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications

Microelectronic engineering, 2007-09, Vol.84 (9), p.2398-2403

2007

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Dry etching device quality high-κ GaxGdyOz gate oxide in SiCl4 chemistry for low resistance ohmic contact realisation in fabricating III-V MOSFETs

Microelectronic engineering, 2010-05, Vol.87 (5-8), p.1587-1589

2010

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180 nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425 μS/μm

Electronics letters, 2007-04, Vol.43 (9), p.543-545

2007

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EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices

Journal of physics. Conference series, 2008-08, Vol.126 (1), p.012053

2008

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Dry etching of a device quality high-k GaxGdyOz gate oxide in CH4/H2-O2 chemistry for the fabrication of III-V MOSFETs

Microelectronic engineering, 2007-05, Vol.84 (5-8), p.1124-1127

2007

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Compound semiconductors on silicon for future generation VLSI

2010 IEEE International SOI Conference (SOI), 2010, p.1-3

2010

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High-Speed E-Mode InAs QW MOSFETs With \hbox \hbox Insulator for Future RF Applications

IEEE electron device letters, 2013-02, Vol.34 (2), p.196-198

2013

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Fabrication module development for the realisation of III-V MOSFET devices

Hill, R J W

2006

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(Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic

ECS transactions, 2012, Vol.45 (6), p.179-184

2012

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Review of Current Status of III-V MOSFETs

ECS transactions, 2009, Vol.19 (5), p.275-286

2009

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CMOS Scaling with III-V Channels for Improved Performance and Low Power

ECS transactions, 2011, Vol.35 (3), p.335-344

2011

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Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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Challenges of III-V materials in advanced CMOS logic

Proceedings of Technical Program of 2012 VLSI Technology, System and Application, 2012, p.1-2

2012

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180nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425muS/mum

Electronics letters, 2007-04, Vol.43 (9), p.543-545

2007

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180 nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425 µS/µm

Electronics letters, 2007-04, Vol.43 (9), p.1

2007

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1 µm gate length, In^sub 0.75^Ga^sub 0.25^As channel, thin body n-MOSFET on InP substrate with transconductance of 737 µS/µm

Electronics letters, 2008-03, Vol.44 (7), p.1

2008

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180 nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425 mu S/ mu m

Electronics letters, 2007-04, Vol.43 (9), p.1-1

2007

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1 mu m gate length, In sub( 0.75)Ga sub( 0.25)As channel, thin body n-MOSFET on InP substrate with transconductance of 737 mu S/ mu m

Electronics letters, 2008-03, Vol.44 (7), p.1-1

2008

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1 μm gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 μS/μm

Electronics letters, 2008, Vol.44 (7), p.498-500

2008

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InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax

2012 Symposium on VLSI Technology (VLSIT), 2012, p.179-180

2012

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Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

IEEE transactions on nanotechnology, 2007-01, Vol.6 (1), p.106

2007

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Fabrication module development for the realisation of III-V MOSFET devices

Hill, R J. W

2006

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High Mobility III-V MOSFETs For RF and Digital Applications

2007 IEEE International Electron Devices Meeting, 2007, p.621-624

2007

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Ultra low contact resistivity (−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III-V fin TLM structure fabricated with III-V on Si substrates

2014 IEEE International Electron Devices Meeting, 2014, p.32.4.1-32.4.4

2014

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A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III-V MOSFETs

Simulation of implant free III-V MOSFETs for high performance low power Nano-CMOS applications

Dry etching device quality high-κ GaxGdyOz gate oxide in SiCl4 chemistry for low resistance ohmic contact realisation in fabricating III-V MOSFETs

180 nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425 μS/μm

EFTEM and EELS SI: tools for investigating the effects of etching processes for III-V MOSFET devices

Dry etching of a device quality high-k GaxGdyOz gate oxide in CH4/H2-O2 chemistry for the fabrication of III-V MOSFETs

Compound semiconductors on silicon for future generation VLSI

High-Speed E-Mode InAs QW MOSFETs With \hbox \hbox Insulator for Future RF Applications

Fabrication module development for the realisation of III-V MOSFET devices

(Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic

Review of Current Status of III-V MOSFETs

CMOS Scaling with III-V Channels for Improved Performance and Low Power

Sub-100 nm regrown S/D Gate-Last In0.7Ga0.3As QW MOSFETs with μn,eff > 5,500 cm2/V-s

Challenges of III-V materials in advanced CMOS logic

180nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425muS/mum

180 nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425 µS/µm

1 µm gate length, In^sub 0.75^Ga^sub 0.25^As channel, thin body n-MOSFET on InP substrate with transconductance of 737 µS/µm

180 nm metal gate, high-k dielectric, implant-free III-V MOSFETs with transconductance of over 425 mu S/ mu m

1 mu m gate length, In sub( 0.75)Ga sub( 0.25)As channel, thin body n-MOSFET on InP substrate with transconductance of 737 mu S/ mu m

1 μm gate length, In0.75Ga0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737 μS/μm

InAs quantum-well MOSFET (Lg = 100 nm) with record high gm, fT and fmax

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

Fabrication module development for the realisation of III-V MOSFET devices

High Mobility III-V MOSFETs For RF and Digital Applications

Ultra low contact resistivity (−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III-V fin TLM structure fabricated with III-V on Si substrates

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