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Evaluation of blood pressure estimation models based on pulse arrival time

Computers & electrical engineering, 2020-06, Vol.84, p.106616-15, Article 106616

2020

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Efficient micro data centres deployment for mobile healthcare monitoring systems in IoT urban scenarios

Journal of simulation : JOS, 2022-11, Vol.16 (6), p.589-603

2022

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Runtime data center temperature prediction using Grammatical Evolution techniques

Applied soft computing, 2016-12, Vol.49, p.94-107

2016

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HackRF + GNU Radio: A software-defined radio to teach communication theory

International journal of electrical engineering & education, 2023-01, Vol.60 (1), p.23-40

2023

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Multispeculative Addition Applied to Datapath Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-12, Vol.31 (12), p.1817-1830

2012

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Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks

IEEE transactions on computers, 2019-05, Vol.68 (5), p.660-675

2019

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Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer

Digital signal processing, 2014-10, Vol.33, p.191-205

2014

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Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials

Integration (Amsterdam), 2013-03, Vol.46 (2), p.197-210

2013

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Placement by thermodynamic simulated annealing

Physics letters. A, 2003-10, Vol.317 (5), p.415-423

2003

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Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark

Simulation (San Diego, Calif.), 2017-06, Vol.93 (6), p.459-476

2017

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Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials

IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1388-1393

2006

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A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-03, Vol.35 (3), p.419-432

2016

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A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-03, Vol.30 (3), p.350-363

2011

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A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

Integration (Amsterdam), 2013-03, Vol.46 (2), p.119-130

2013

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Ultra-low-power adder stage design for exascale floating point units

ACM transactions on embedded computing systems, 2014-03, Vol.13 (3s), p.1-24

2014

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Annealing placement by thermodynamic combinatorial optimization

ACM transactions on design automation of electronic systems, 2004-07, Vol.9 (3), p.310-332

2004

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A Modular Low-Complexity ECG Delineation Algorithm for Real-Time Embedded Systems

IEEE journal of biomedical and health informatics, 2018-03, Vol.22 (2), p.429-441

2018

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Exploring the energy efficiency of Multispeculative Adders

2013 IEEE 31st International Conference on Computer Design (ICCD), 2013, p.309-315

2013

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A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths

IEEE transactions on circuits and systems. I, Regular papers, 2019-02, Vol.66 (2), p.742-755

2019

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Improving circuit performance with multispeculative additive trees in high-level synthesis

Microelectronics, 2014-11, Vol.45 (11), p.1470-1479

2014

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Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks

2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, p.617-622

2018

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Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 2003, p.151-160

2003

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A slack-based approach to efficiently deploy radix 8 booth multipliers

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.1153-1158

2017

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Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-01, Vol.28 (1), p.60-73

2009

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Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 2003, p.617-627

2003

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Evaluation of blood pressure estimation models based on pulse arrival time

Efficient micro data centres deployment for mobile healthcare monitoring systems in IoT urban scenarios

Runtime data center temperature prediction using Grammatical Evolution techniques

HackRF + GNU Radio: A software-defined radio to teach communication theory

Multispeculative Addition Applied to Datapath Synthesis

Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks

Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer

Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials

Placement by thermodynamic simulated annealing

Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark

Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials

A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis

A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths

Ultra-low-power adder stage design for exascale floating point units

Annealing placement by thermodynamic combinatorial optimization

A Modular Low-Complexity ECG Delineation Algorithm for Real-Time Embedded Systems

Exploring the energy efficiency of Multispeculative Adders

A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths

Improving circuit performance with multispeculative additive trees in high-level synthesis

Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks

Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization

A slack-based approach to efficiently deploy radix 8 booth multipliers

Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications

Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis

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