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Modular Over‐the‐air Software Updates for Safety‐critical Real‐time Systems

Insight (International Council on Systems Engineering), 2022-12, Vol.25 (4), p.85-88

2022

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Leakage Models for High-Level Power Estimation

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-08, Vol.37 (8), p.1627-1639

2018

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A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms

Embedded Computer Systems: Architectures, Modeling, and Simulation, p.250-263

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Voltage- and ABB-island optimization in high level synthesis

International Symposium on Low Power Electronics and Design: Proceedings of the 2007 international symposium on Low power electronics and design; 27-29 Aug. 2007, 2007, p.153-158

2007

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Accelerating and pruning CNNs for semantic segmentation on FPGA

Proceedings of the 59th ACM/IEEE Design Automation Conference, 2022, p.145-150

2022

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RT level timing modeling for aging prediction

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.297-300

2016

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Hardware Execution Time Prediction for Neural Network Layers

Machine Learning and Principles and Practice of Knowledge Discovery in Databases, p.582-593

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Efficient NBTI modeling technique considering recovery effects

2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2014, p.177-182

2014

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Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p.171-180

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Analysis of NBTI effects on high frequency digital circuits

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.223-228

2016

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Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 2006, p.56-65

2006

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Using Network Architecture Search for Optimizing Tensor Compression

Designing Modern Embedded Systems: Software, Hardware, and Applications, 2023, Vol.AICT-669, p.139-150

2023

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Understanding Ageing Mechanisms

Ageing of Integrated Circuits, p.3-34

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Phase Space Based NBTI Model

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p.52-61

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Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction

Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design, 2009, p.33-38

2009

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An Embedded CNN Implementation for On-Device ECG Analysis

2020 IEEE International Conference on Pervasive Computing and Communications Workshops (PerCom Workshops), 2020, p.1-6

2020

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RTL power modeling and estimation of sleep transistor based power gating

Journal of Embedded Computing, 2009, Vol.3 (3), p.189-196

2009

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Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms

DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023, p.79-86

2023

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Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.919-922

2007

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RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, p.278-287

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Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, p.220-225

2006

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Timing modeling at RT-level by separation of design- and stress related aging impacts

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, p.1-6

2017

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User dependent aging prediction model for automotive controllers with power electronics

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, p.1-6

2017

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On leakage currents: sources and reduction for transistors, gates, memories and digital systems

Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08), 2008, p.349-350

2008

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System Level Optimization of Static Power Consumption in Nano-CMOS Circuits

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems, 2007, p.169-171

Helms, D.

2007

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Modular Over‐the‐air Software Updates for Safety‐critical Real‐time Systems

Leakage Models for High-Level Power Estimation

A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms

Voltage- and ABB-island optimization in high level synthesis

Accelerating and pruning CNNs for semantic segmentation on FPGA

RT level timing modeling for aging prediction

Hardware Execution Time Prediction for Neural Network Layers

Efficient NBTI modeling technique considering recovery effects

Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components

Analysis of NBTI effects on high frequency digital circuits

Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage

Using Network Architecture Search for Optimizing Tensor Compression

Understanding Ageing Mechanisms

Phase Space Based NBTI Model

Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction

An Embedded CNN Implementation for On-Device ECG Analysis

RTL power modeling and estimation of sleep transistor based power gating

Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms

Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating

Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation

Timing modeling at RT-level by separation of design- and stress related aging impacts

User dependent aging prediction model for automotive controllers with power electronics

On leakage currents: sources and reduction for transistors, gates, memories and digital systems

System Level Optimization of Static Power Consumption in Nano-CMOS Circuits

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