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Providing fault tolerance through invasive computing

Information technology (Munich, Germany), 2016-12, Vol.58 (6), p.309-328

2016

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Network Interface with Task Spawning Support for NoC-Based DSM Architectures

Architecture of Computing Systems – ARCS 2015, p.186-198

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Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Computers & electrical engineering, 2013-11, Vol.39 (8), p.2603-2622

2013

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Efficient task spawning for shared memory and message passing in many-core architectures

Journal of systems architecture, 2017-06, Vol.77, p.72-82

2017

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A scalable and adaptive network on chip for many-core architectures

Heißwolf, Jan

2014

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Virtual networks -- distributed communication resource management

ACM transactions on reconfigurable technology and systems, 2013-07, Vol.6 (2), p.1

2013

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Virtual networks -- distributed communication resource management

ACM transactions on reconfigurable technology and systems, 2013-07, Vol.6 (2), p.1-14

2013

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Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012, p.234-241

2012

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AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections

2013 Euromicro Conference on Digital System Design, 2013, p.761-768

2013

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Hybrid interconnect design for heterogeneous hardware accelerators

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.843-846

2013

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CAP: Communication Aware Programming

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6

2014

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Invasive manycore architectures

17th Asia and South Pacific Design Automation Conference, 2012, p.193-200

2012

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IEEE_Xplore

A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling

2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications, 2012, p.625-632

2012

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Hardware/software debugging of large scale many-core architectures

2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI), 2014, p.1-7

2014

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Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers

2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 2013, p.1-6

2013

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NoC simulation in heterogeneous architectures for PGAS programming model

Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, 2013, p.77-85

2013

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A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers

2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI), 2015, p.1-6

2015

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A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 2011, p.150-157

2011

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IEEE_Xplore

Architecture design space exploration of run-time scalable issue-width processors

2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2011, p.77-84

2011

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IEEE_Xplore

Fault-tolerant communication in invasive networks on chip

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2015, p.1-8

2015

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Hardware Supported Adaptive Data Collection for Networks on Chip

2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum, 2013, p.153-162

2013

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Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013, p.1-8

2013

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IEEE_Xplore

Hybrid interconnect design for heterogeneous hardware accelerators

Proceedings of the Conference on Design, Automation and Test in Europe, 2013, p.843-846

2013

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Hardware prototyping of novel invasive multicore architectures

17th Asia and South Pacific Design Automation Conference, 2012, p.201-206

2012

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IEEE_Xplore

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Providing fault tolerance through invasive computing

Network Interface with Task Spawning Support for NoC-Based DSM Architectures

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Efficient task spawning for shared memory and message passing in many-core architectures

A scalable and adaptive network on chip for many-core architectures

Virtual networks -- distributed communication resource management

Virtual networks -- distributed communication resource management

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections

Hybrid interconnect design for heterogeneous hardware accelerators

CAP: Communication Aware Programming

Invasive manycore architectures

A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling

Hardware/software debugging of large scale many-core architectures

Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers

NoC simulation in heterogeneous architectures for PGAS programming model

A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers

A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors

Architecture design space exploration of run-time scalable issue-width processors

Fault-tolerant communication in invasive networks on chip

Hardware Supported Adaptive Data Collection for Networks on Chip

Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation

Hybrid interconnect design for heterogeneous hardware accelerators

Hardware prototyping of novel invasive multicore architectures

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