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High-performance interconnects: an integration overview

Proceedings of the IEEE, 2001-05, Vol.89 (5), p.586-601

2001

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Air-gap formation during IMD deposition to lower interconnect capacitance

IEEE electron device letters, 1998-01, Vol.19 (1), p.16-18

1998

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Integrated CVD–PVD Al plug processing for sub-half micron features

Thin solid films, 1998-05, Vol.320 (1), p.52-57

1998

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Statistics of electromigration early failures in Cu/oxide dual-damascene interconnects

2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167), 2001, p.341-349

2001

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Electromigration reliability of dual damascene Cu/CVD SiOC interconnects

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461), 2001, p.266-268

2001

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A Novel Process for Fabricating Conformal and Stable TiN‐Based Barrier Films

Journal of the Electrochemical Society, 1996-12, Vol.143 (12), p.L279-L280

1996

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Electromigration reliability improvement of W-plug vias by titanium layering

Proceedings of 1994 IEEE International Reliability Physics Symposium, 1994, p.173-177

1994

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Conductivity and the Microwave Properties of 81-Permalloy Thin Films (Correspondence)

IEEE transactions on microwave theory and techniques, 1971-01, Vol.19 (1), p.113-116

1971

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Thermal stability of Al/barrier/TiSi x multilayer structures

Thin solid films, 1998, Vol.320 (1), p.20-25

1998

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Thermal stability of Al/barrier/TiSix multilayer structures

Thin solid films, 1998-05, Vol.320 (1), p.20-25

1998

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An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

IEEE journal of solid-state circuits, 1988-10, Vol.23 (5), p.1041-1047

1988

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Line width dependence of copper resistivity

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461), 2001, p.227-229

2001

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Chapter 2 - Scaled MOS and Bipolar Technologies for VLSI

VLSI Electronics Microstructure Science, 1983, Vol.7, p.39-127

1983

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MOS and bipolar VLSI technologies using electron-beam lithography

Proceedings of the IEEE, 1983-01, Vol.71 (5), p.612-639

1983

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Optimization of annealing conditions for dual damascene Cu microstructures and via chain yields

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001, p.139-140

2001

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Annealing impact on damascene Cu resistivity and microstructures

2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443), 2001, Vol.1, p.400-404 vol.1

2001

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Implementation of low-dielectric-constant materials for ULSI circuit performance improvement

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 1995, p.164-168

1995

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Highly porous interlayer dielectric for interconnect capacitance reduction

1995 Symposium on VLSI Technology. Digest of Technical Papers, 1995, p.61-62

1995

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CoSi/sub 2/ with low diode leakage and low sheet resistance at 0.065 /spl mu/m gate length

International Electron Devices Meeting. IEDM Technical Digest, 1997, p.107-110

1997

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A planarized multilevel interconnect scheme with embedded low-dielectric-constant polymers for sub-quarter-micron applications

Proceedings of 1994 VLSI Technology Symposium, 1994, p.73-74

1994

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Damascene integration of copper and ultra-low-k xerogel for high performance interconnects

International Electron Devices Meeting. IEDM Technical Digest, 1997, p.936-938

1997

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E-beam fabrication of bipolar VLSI logic, including a ∼ 5K gate 16-bit I2L microprocessor

1981 International Electron Devices Meeting, 1981, p.528-531

1981

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An integrated low resistance aluminum plug and low-k polymer dielectric for high performance 0.25 /spl mu/m interconnects

1996 Symposium on VLSI Technology. Digest of Technical Papers, 1996, p.86-87

1996

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Ion metal plasma (IMP) deposited titanium liners for 0.25/0.18 /spl mu/m multilevel interconnections

International Electron Devices Meeting. Technical Digest, 1996, p.357-360

1996

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An 0.8 µm CMOS technology for high performance logic applications

1987 International Electron Devices Meeting, 1987, p.362-365

1987

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High-performance interconnects: an integration overview

Air-gap formation during IMD deposition to lower interconnect capacitance

Integrated CVD–PVD Al plug processing for sub-half micron features

Statistics of electromigration early failures in Cu/oxide dual-damascene interconnects

Electromigration reliability of dual damascene Cu/CVD SiOC interconnects

A Novel Process for Fabricating Conformal and Stable TiN‐Based Barrier Films

Electromigration reliability improvement of W-plug vias by titanium layering

Conductivity and the Microwave Properties of 81-Permalloy Thin Films (Correspondence)

Thermal stability of Al/barrier/TiSi x multilayer structures

Thermal stability of Al/barrier/TiSix multilayer structures

An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

Line width dependence of copper resistivity

Chapter 2 - Scaled MOS and Bipolar Technologies for VLSI

MOS and bipolar VLSI technologies using electron-beam lithography

Optimization of annealing conditions for dual damascene Cu microstructures and via chain yields

Annealing impact on damascene Cu resistivity and microstructures

Implementation of low-dielectric-constant materials for ULSI circuit performance improvement

Highly porous interlayer dielectric for interconnect capacitance reduction

CoSi/sub 2/ with low diode leakage and low sheet resistance at 0.065 /spl mu/m gate length

A planarized multilevel interconnect scheme with embedded low-dielectric-constant polymers for sub-quarter-micron applications

Damascene integration of copper and ultra-low-k xerogel for high performance interconnects

E-beam fabrication of bipolar VLSI logic, including a ∼ 5K gate 16-bit I2L microprocessor

An integrated low resistance aluminum plug and low-k polymer dielectric for high performance 0.25 /spl mu/m interconnects

Ion metal plasma (IMP) deposited titanium liners for 0.25/0.18 /spl mu/m multilevel interconnections

An 0.8 µm CMOS technology for high performance logic applications

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