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A 10-GS/s 8-bit 2850-μm 2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC
IEEE journal of solid-state circuits, 2022-12, Vol.57 (12), p.3757-3767
2022
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A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC
IEEE journal of solid-state circuits, 2022-12, Vol.57 (12), p.3757-3767
2022
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A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation
IEEE journal of solid-state circuits, 2018-06, Vol.53 (6), p.1765-1779
2018
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Fast Static Characterization of Residual-Based ADCs
IEEE transactions on circuits and systems. II, Express briefs, 2013-11, Vol.60 (11), p.746-750
2013
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A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis
ACM transactions on design automation of electronic systems, 2021-09, Vol.26 (5), p.1-22
2021
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A 10GS/s 8b 25fJ/c-s 2850um2 Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology
2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.160-162
2022
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A Novel Multi-Objective Optimization Framework for Analog Circuit Customization
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-2
2024
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Transfer learning with bayesian optimization-aided sampling for efficient AMS circuit modeling
2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9
2020
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A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS
IEEE transactions on circuits and systems. I, Regular papers, 2017-06, Vol.64 (6), p.1354-1367
2017
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A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells
2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, p.1-4
2019
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Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling
2021 58th ACM/IEEE Design Automation Conference (DAC), 2021, p.505-510
2021
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From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2021, p.1-9
2021
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A low-power low-offset dynamic comparator for analog to digital converters
Microelectronics, 2014-02, Vol.45 (2), p.256-262
2014
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TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022, p.526-531
2022
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Step response analysis of third order OpAmps With slew-rate
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), 2013, p.62-63
2013
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Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 2022, p.100-107
2022
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A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS
2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016, p.1-2
2016
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