UB Paderborn / Katalog / Suche / in CDI

Education on Electronic Packaging in Department of Electronic and Electrical Engineering

Journal of The Japan Institute of Electronics Packaging, 2021-09, Vol.24 (6), p.484-487

Hashizume, Masaki

2021

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Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design

2018 IEEE 27th Asian Test Symposium (ATS), 2018, p.7-12

2018

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Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (12), p.2842-2850

2017

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A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

IEICE Transactions on Information and Systems, 2018/08/01, Vol.E101.D(8), pp.2053-2063

2018

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Testing of Weak Open Defects in Interconnects Using Boundary Scan

Journal of The Japan Institute of Electronics Packaging, 2024-07, Vol.27 (4), p.288-293

2024

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SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2013, Vol.E96.A (12), p.2561-2567

2013

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On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

IEICE Transactions on Information and Systems, 2013/09/01, Vol.E96.D(9), pp.1986-1993

2013

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A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

IEICE Transactions on Information and Systems, 2016/11/01, Vol.E99.D(11), pp.2723-2733

2016

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Delay Testable Design Using Modified Boundary Scan

Journal of The Japan Institute of Electronics Packaging, 2021-11, Vol.24 (7), p.663-667

2021

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Modified PRPG for Test Data Reduction Using BAST Structure

Journal of Signal Processing, 2017/07/20, Vol.21(4), pp.125-128

2017

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Performance evaluation of an event-driven silicon-on-insulator pixel detector “XRPIX8.5” for cosmic MeV gamma-ray observation

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2024-09, p.169911, Article 169911

2024

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Lowering the energy threshold using a plastic scintillator and radiation-damaged SiPMs

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2024-04, Vol.1061, p.169097, Article 169097

2024

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X-ray evaluation of the CMOS image sensor IU233N5-Z and readout the scintillation light

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2024-09, Vol.1066, p.169585, Article 169585

2024

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An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs

IEICE Transactions on Information and Systems, 2013/09/01, Vol.E96.D(9), pp.2026-2030

2013

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Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

IEICE Transactions on Information and Systems, 2010/01/01, Vol.E93.D(1), pp.10-16

2010

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Performance evaluation of the high-voltage CMOS active pixel sensor AstroPix for gamma-ray space telescopes

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2024-11, Vol.1068, p.169762, Article 169762

2024

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Electrical Test Method for Interconnect Open Defects in 3D ICs

TRANSACTIONS OF THE JAPAN INSTITUTE OF ELECTRONICS PACKAGING, 2012, Vol.5 (1), p.26-33

2012

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Propagation Delay Analysis of a Soft Open Defect inside a TSV

TRANSACTIONS OF THE JAPAN INSTITUTE OF ELECTRONICS PACKAGING, 2011, Vol.4 (1), p.119-126

2011

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Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators

2022 IEEE 31st Asian Test Symposium (ATS), 2022, p.49-53

2022

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Fault Securing Techniques for Yield and Reliability Enhancement of RRAM

2022 IEEE 31st Asian Test Symposium (ATS), 2022, p.13-18

2022

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Open Defect Detection in Assembled Circuit Boards With Built-In Relaxation Oscillators

IEEE transactions on components, packaging, and manufacturing technology (2011), 2021-06, Vol.11 (6), p.931-943

2021

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Fault-Aware Dependability Enhancement Techniques for Flash Memories

IEEE transactions on very large scale integration (VLSI) systems, 2020-03, Vol.28 (3), p.634-645

2020

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Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards

IEEE transactions on components, packaging, and manufacturing technology (2011), 2020-05, Vol.10 (5), p.895-907

2020

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Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories

IEEE transactions on very large scale integration (VLSI) systems, 2016-08, Vol.24 (8), p.2726-2734

2016

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A Built-In Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

Applied Mechanics and Materials, 2015-05, Vol.761 (Recent Technologies in Design, Management and Manufacturing), p.202-207

2015

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Education on Electronic Packaging in Department of Electronic and Electrical Engineering

Test Time Reduction on Testing Delay Faults in 3D ICs Using Boundary Scan Design

Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Testing of Weak Open Defects in Interconnects Using Boundary Scan

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan

A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs

Delay Testable Design Using Modified Boundary Scan

Modified PRPG for Test Data Reduction Using BAST Structure

Performance evaluation of an event-driven silicon-on-insulator pixel detector “XRPIX8.5” for cosmic MeV gamma-ray observation

Lowering the energy threshold using a plastic scintillator and radiation-damaged SiPMs

X-ray evaluation of the CMOS image sensor IU233N5-Z and readout the scintillation light

An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs

Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

Performance evaluation of the high-voltage CMOS active pixel sensor AstroPix for gamma-ray space telescopes

Electrical Test Method for Interconnect Open Defects in 3D ICs

Propagation Delay Analysis of a Soft Open Defect inside a TSV

Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators

Fault Securing Techniques for Yield and Reliability Enhancement of RRAM

Open Defect Detection in Assembled Circuit Boards With Built-In Relaxation Oscillators

Fault-Aware Dependability Enhancement Techniques for Flash Memories

Open Defect Detection Not Utilizing Boundary Scan Flip-Flops in Assembled Circuit Boards

Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories

A Built-In Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

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