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A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems

Chronic diseases and translational medicine, 2023-07, Vol.17 (3-4), p.141-148

2023

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Signal Integrity in High Speed 3D IC Design- A Case Study

2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, p.1-5

2021

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A supply-insensitive self-regulating CMOS ring oscillator

2015 International SoC Design Conference (ISOCC), 2015, p.71-72

2015

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Development, Implementation, Assessment of a Web-based Circuit Solver for Teaching Basic Electrical Circuits Theory

International Journal of Online and Biomedical Engineering, 2015-01, Vol.11 (4), p.55

2015

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A CMOS High Resolution Multi-Edge Delay Generator

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015, p.1-4

2015

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Impact of Crosstalk on Signal Integrity of TSVs in 3D Integrated Circuits

Advances in Science, Technology and Engineering Systems Journal (ASTESJ), 2018-01, Vol.3 (1), p.109-114

2018

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On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs

Advances in Science, Technology and Engineering Systems Journal (ASTESJ), 2017-07, Vol.2 (3), p.1260-1265

2017

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A study of characterizing crosstalk effects in 3-D vias

2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 2017, p.1-4

2017

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Oscillation ring testing methodology of TSVs in 3D stacked ICs

2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, p.1-4

2016

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The incidence of hypoglycaemia in Muslim patients with type 2 diabetes treated with sitagliptin or a sulphonylurea during Ramadan: a randomised trial

International journal of clinical practice (Esher), 2011-11, Vol.65 (11), p.1132-1140

2011

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A sub-1V CMOS voltage reference generator

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.901-904

2011

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A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter

Informatica (Ljubljana), 2011-06, Vol.35 (2), p.211-219

2011

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Analytical Study of the Expected Number of Hops in Wireless Ad Hoc Network

Wireless Algorithms, Systems, and Applications, 2008, Vol.5258, p.63-71

2008

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High speed digital CMOS divide-by-N fequency divider

2008 IEEE International Symposium on Circuits and Systems, 2008, p.592-595

2008

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Time delay measurement and voltage reference circuits compatible for embedded test in three-dimensional stacked ICS

Harb, Shadi M

2010

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Low-Power Content Addressable Memory With Read/ Write and Matched Mask Ports

Integrated Circuit and System Design, 2007, Vol.4644, p.75-85

2007

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On-chip jitter measurement architecture using a delay-locked loop with vernier delay line, to the order of giga hertz

Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2011, 2011, p.502-506

2011

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A low-power CAM using a 12-transistor design cell

2007 IFIP International Conference on Very Large Scale Integration, 2007, p.264-269

2007

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High speed I/O and thermal effect characterization of 3D stacked ICs

2009 IEEE International Conference on 3D System Integration, 2009, p.1-5

2009

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A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems

Signal Integrity in High Speed 3D IC Design- A Case Study

A supply-insensitive self-regulating CMOS ring oscillator

Development, Implementation, Assessment of a Web-based Circuit Solver for Teaching Basic Electrical Circuits Theory

A CMOS High Resolution Multi-Edge Delay Generator

Impact of Crosstalk on Signal Integrity of TSVs in 3D Integrated Circuits

On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs

A study of characterizing crosstalk effects in 3-D vias

Oscillation ring testing methodology of TSVs in 3D stacked ICs

The incidence of hypoglycaemia in Muslim patients with type 2 diabetes treated with sitagliptin or a sulphonylurea during Ramadan: a randomised trial

A sub-1V CMOS voltage reference generator

A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter

Analytical Study of the Expected Number of Hops in Wireless Ad Hoc Network

High speed digital CMOS divide-by-N fequency divider

Time delay measurement and voltage reference circuits compatible for embedded test in three-dimensional stacked ICS

Low-Power Content Addressable Memory With Read/ Write and Matched Mask Ports

On-chip jitter measurement architecture using a delay-locked loop with vernier delay line, to the order of giga hertz

A low-power CAM using a 12-transistor design cell

High speed I/O and thermal effect characterization of 3D stacked ICs

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