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Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems

Scientific reports, 2024-01, Vol.14 (1), p.1339-1339, Article 1339

2024

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Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver

Journal of applied physics, 2015-05, Vol.117 (17)

2015

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Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

IEEE transaction on neural networks and learning systems, 2023-12, Vol.34 (12), p.10999-11005

2023

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Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Proceedings of the IEEE, 2016-10, Vol.104 (10), p.1844-1863

2016

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Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware

IEICE Transactions on Information and Systems, 2024/08/01, Vol.E107.D(8), pp.958-965

2024

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Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow

IEICE Transactions on Information and Systems, 2021/08/01, Vol.E104.D(8), pp.1111-1120

2021

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Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

Japanese Journal of Applied Physics, 2022-05, Vol.61 (SC), p.SC1083

2022

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Efficient CMOS Invertible Logic Using Stochastic Computing

IEEE transactions on circuits and systems. I, Regular papers, 2019-06, Vol.66 (6), p.2263-2274

2019

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Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure

Japanese Journal of Applied Physics, 2019-04, Vol.58 (SB), p.SBBB10

2019

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Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic

IEEE transactions on magnetics, 2014-11, Vol.50 (11), p.1-4

2014

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Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits

Japanese Journal of Applied Physics, 2022-05, Vol.61 (SC), p.SC1035

2022

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High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter

IEEE transactions on very large scale integration (VLSI) systems, 2020-10, Vol.28 (10), p.2171-2181

2020

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Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1116-1128

2021

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Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

IEEE transactions on circuits and systems. I, Regular papers, 2021-01, Vol.68 (1), p.67-76

2021

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Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Japanese Journal of Applied Physics, 2021-05, Vol.60 (SB), p.SBBB02

2021

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Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware

Japanese Journal of Applied Physics, 2019-04, Vol.58 (SB), p.SBBB01

2019

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In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning

IEEE transactions on circuits and systems. I, Regular papers, 2020-05, Vol.67 (5), p.1541-1550

2020

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Impact of MTJ-based nonvolatile circuit techniques for energy-efficient binary neural network hardware

Japanese Journal of Applied Physics, 2020-05, Vol.59 (5), p.50602

2020

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Gabor Filter Based on Stochastic Computation

IEEE signal processing letters, 2015-09, Vol.22 (9), p.1224-1228

2015

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High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

IEEE journal on emerging and selected topics in circuits and systems, 2023-03, Vol.13 (1), p.1-1

2023

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Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

Memories - Materials, Devices, Circuits and Systems, 2023-07, Vol.4, p.100035, Article 100035

2023

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Self-Adaptive Gate Control for Efficient Escape from Local Minimum Energy on Invertible Logic

IEEE access, 2023-01, Vol.11, p.1-1

2023

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Design of a low-power nonvolatile flip-flop using three-terminal magnetic-tunnel-junction-based self-terminated mechanism

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S), p.4-04CN06

2017

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Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Applied physics express, 2008-09, Vol.1, p.91301

2008

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Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems

Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver

Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing

Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

Efficient CMOS Invertible Logic Using Stochastic Computing

Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure

Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic

Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits

High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware

In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning

Impact of MTJ-based nonvolatile circuit techniques for energy-efficient binary neural network hardware

Gabor Filter Based on Stochastic Computation

High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians

Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

Self-Adaptive Gate Control for Efficient Escape from Local Minimum Energy on Invertible Logic

Design of a low-power nonvolatile flip-flop using three-terminal magnetic-tunnel-junction-based self-terminated mechanism

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

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