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eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters

IEEE journal of solid-state circuits, 2024-06, Vol.59 (6), p.1950-1961

2024

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Advances in Microprocessor Cache Architectures Over the Last 25 Years

IEEE MICRO, 2021-11, Vol.41 (6), p.78-88

2021

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13.3 A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.214-216

2019

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Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.112-113

2022

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A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.146-151

2006

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Session 7 overview: Non-volatile memory solutions: Memory subcommittee

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.126-127

2015

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A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.150-158

2013

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Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.751-758

2010

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A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.150-157

2015

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16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.248-250

2021

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SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.895-901

2005

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An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees

2018 IEEE International Solid-State Circuits Conference - (ISSCC), 2018, p.486-487

2018

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Embedded Memories for Silicon-In-Package: Optimization of Memory Subsystem from IoT to Machine Learning

2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2019, p.1-1

Hamzaoglu, Fatih

2019

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Embedded Memories for Silicon-ln-Package: Optimization of Memory Subsystem from loT to Machine Learning

2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2019, p.1-1

Hamzaoglu, Fatih

2019

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Low-Power SRAMs in Nanoscale CMOS Technologies

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.145-151

2008

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A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.103-110

2010

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eNVM MRAM Retention Reliability Modeling in 22FFL FinFET Technology

2019 IEEE International Reliability Physics Symposium (IRPS), 2019, p.1-3

2019

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A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.76-84

2011

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A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.148-154

2009

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Low-Power SRAMs in Nanoscale CMOS Technologies : Device technologies and circuit techniques for power management

IEEE transactions on electron devices, 2008, Vol.55 (1), p.145-151

2008

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A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE journal of solid-state circuits, 2008, Vol.43 (1), p.172-179

2008

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13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.212-214

2019

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Process, Temperature, and Supply-Noise Tolerant 45 ~nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits

IEEE journal of solid-state circuits, 2009-04, Vol.44 (4), p.1199-1208

2009

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F2: Memory trends: From big data to wearable devices

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-2

2015

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eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters

Advances in Microprocessor Cache Architectures Over the Last 25 Years

13.3 A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique

Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Session 7 overview: Non-volatile memory solutions: Memory subcommittee

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS

Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees

Embedded Memories for Silicon-In-Package: Optimization of Memory Subsystem from IoT to Machine Learning

Embedded Memories for Silicon-ln-Package: Optimization of Memory Subsystem from loT to Machine Learning

Low-Power SRAMs in Nanoscale CMOS Technologies

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

eNVM MRAM Retention Reliability Modeling in 22FFL FinFET Technology

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

Low-Power SRAMs in Nanoscale CMOS Technologies : Device technologies and circuit techniques for power management

A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

13.2 A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V

Process, Temperature, and Supply-Noise Tolerant 45 ~nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits

F2: Memory trends: From big data to wearable devices

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