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Enhanced statistical detection of random telegraph noise in frequency and time domain

Solid-state electronics, 2022-08, Vol.194, p.108320, Article 108320

2022

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Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure

2023 35th International Conference on Microelectronic Test Structure (ICMTS), 2023, p.1-6

2023

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Universality of trap-induced mobility fluctuations between 1/f noise and random telegraph noise in nanoscale FD-SOI MOSFETs

Applied physics letters, 2023-06, Vol.122 (23)

2023

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Applicability of the Carrier Number Fluctuations Model for Random Telegraph Noise of Nanoscale MOSFETs Operating in Saturation

2023 International Conference on Noise and Fluctuations (ICNF), 2023, p.1-4

2023

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Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature

Solid-state electronics, 2021-12, Vol.186, p.108071, Article 108071

2021

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Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology

2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2021, p.1-5

2021

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Sub-threshold 10T SRAM bit cell with read/write XY selection

Solid-state electronics, 2015-04, Vol.106, p.1-11

2015

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Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

IEEE transactions on electron devices, 2015-05, Vol.62 (5), p.1574-1579

2015

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Characterization and Modeling of NBTI in Nanoscale UltraThin Body UltraThin Box FD-SOI MOSFETs

IEEE transactions on electron devices, 2016-12, Vol.63 (12), p.4913-4918

2016

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Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

IEEE transactions on electron devices, 2016-08, Vol.63 (8), p.3222-3228

2016

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Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

IEEE transactions on electron devices, 2015-10, Vol.62 (10), p.3117-3124

2015

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New 10V to 1V level shifter based on new N/PMOS high voltage in FDSOI technology

2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 2021, p.1-4

2021

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Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology

Solid-state electronics, 2015-09, Vol.111, p.100-103

2015

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Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications

2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS), 2020, p.1-5

2020

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Performance analysis of multi-VT design solutions in 28nm UTBB FD-SOI technology

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

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New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

2015 IEEE International Reliability Physics Symposium, 2015, p.XT.1.1-XT.1.6

2015

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6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology

Proceedings of 2013 International Conference on IC Design & Technology (ICICDT), 2013, p.89-92

2013

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Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

2013 Proceedings of the ESSCIRC (ESSCIRC), 2013, p.415-418

2013

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Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node

Journal of low-power electronics, 2012-02, Vol.8 (1), p.106-112

2012

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Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012, p.334-337

2012

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Design-in reliability approach for Hot Carrier injection modeling in the context of AMS/RF applications

2011 International Reliability Physics Symposium, 2011, p.5A.5.1-5A.5.7

2011

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65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs

ECS transactions, 2009, Vol.19 (4), p.257-264

2009

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18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs

2022 International Electron Devices Meeting (IEDM), 2022, p.27.2.1-27.2.4

2022

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Electrostatics and channel coupling on 28 nm FD-SOIfor cryogenic applications

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, p.1-4

2020

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Bandgap Engineering in SiGe:C HBTs For Power Amplifier Applications

ECS transactions, 2006, Vol.3 (7), p.913-918

2006

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Enhanced statistical detection of random telegraph noise in frequency and time domain

Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure

Universality of trap-induced mobility fluctuations between 1/f noise and random telegraph noise in nanoscale FD-SOI MOSFETs

Applicability of the Carrier Number Fluctuations Model for Random Telegraph Noise of Nanoscale MOSFETs Operating in Saturation

Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology

Sub-threshold 10T SRAM bit cell with read/write XY selection

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

Characterization and Modeling of NBTI in Nanoscale UltraThin Body UltraThin Box FD-SOI MOSFETs

Study of Hot-Carrier-Induced Traps in Nanoscale UTBB FD-SOI MOSFETs by Low-Frequency Noise Measurements

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

New 10V to 1V level shifter based on new N/PMOS high voltage in FDSOI technology

Dynamic variability in 14nm FD-SOI MOSFETs and transient simulation methodology

Integrated Variability Measurements of 28 nm FDSOI MOSFETs down to 4.2 K for Cryogenic CMOS Applications

Performance analysis of multi-VT design solutions in 28nm UTBB FD-SOI technology

New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node

Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI MOSFETs

Design-in reliability approach for Hot Carrier injection modeling in the context of AMS/RF applications

65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs

18nm FDSOI Enhanced Device Platform for ULP/ULL MCUs

Electrostatics and channel coupling on 28 nm FD-SOIfor cryogenic applications

Bandgap Engineering in SiGe:C HBTs For Power Amplifier Applications

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