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Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function

Japanese Journal of Applied Physics, 2008-06, Vol.47 (6R), p.4385

2008

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Temperature Dependence of Substrate and Drain-Currents in Bulk FinFETs

IEEE transactions on electron devices, 2007-05, Vol.54 (5), p.1259-1264

2007

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The Effect of Adjacent Bit-Line Cell Interference on Random Telegraph Noise in nand Flash Memory Cell Strings

IEEE transactions on electron devices, 2012-12, Vol.59 (12), p.3568-3573

2012

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Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)

IEEE transactions on electron devices, 2007-03, Vol.54 (3), p.537-545

2007

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New Read Schemes Using Boosted Channel Potential of Adjacent Bit-Line Strings in nand Flash Memory

IEEE electron device letters, 2012-08, Vol.33 (8), p.1198-1200

2012

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Highly scalable saddle MOSFET for high-density and high-performance DRAM

IEEE electron device letters, 2005-09, Vol.26 (9), p.690-692

2005

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Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

IEEE electron device letters, 2006-09, Vol.27 (9), p.759-761

2006

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Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure

Japanese Journal of Applied Physics, 2007-10, Vol.46 (10R), p.6589

2007

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Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor

Japanese Journal of Applied Physics, 2006-03, Vol.45 (3R), p.1467

2006

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5-bit/cell Characteristics using mixed program/erase mechanism in recessed channel non-volatile memory cells

Current applied physics, 2010, Vol.10 (1), p.e2-e4

2010

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Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer

Japanese Journal of Applied Physics, 2006-10, Vol.45 (10L), p.L1027

2006

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Two-Bit/Cell Characteristics of Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Devices with Recessed Channel Structure

Japanese Journal of Applied Physics, 2008-04, Vol.47 (4S), p.2687

2008

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Band-to-Band Hot-hole Erase Characteristics of 2-Bit/cell NOR-type Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Cell with Spacer-type Storage Node on Recessed Channel Structure

Japanese Journal of Applied Physics, 2007-09, Vol.46 (9L), p.L798

2007

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A new read method suppressing effect of random telegraph noise in NAND flash memory by using hysteretic characteristic

2013 Symposium on VLSI Technology, 2013, p.T154-T155

2013

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Design of NAND Flash Memory Device by the Fringing Field from a Control Gate

Journal of the Korean Physical Society, 2008, 53(6), , pp.3411-3415

2008

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Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors

IEEE transactions on nanotechnology, 2008-07, Vol.7 (4), p.427-433

2008

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Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias

Journal of the Korean Physical Society, 2007, 51(III), , pp.275-279

2007

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Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

Japanese Journal of Applied Physics, 2007-06, Vol.46 (6R), p.3347

2007

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Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure

2012 International Electron Devices Meeting, 2012, p.9.3.1-9.3.4

2012

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Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2176

2005

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Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

Journal of semiconductor technology and science, 2007-06, Vol.7 (2), p.76-81

2007

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Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias

Journal of the Korean Physical Society, 2007-12, p.275-279

2007

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Dependency of NAND flash memory cells on random dopant fluctuation (RDF) effects

2012 12th Annual Non-Volatile Memory Technology Symposium Proceedings, 2012, p.37-40

2012

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Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

Journal of semiconductor technology and science, 2007, Vol.7 (2), p.76-81

2007

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4-bit/cell charge trapping flash device for high density formed in recess region

2008 IEEE Silicon Nanoelectronics Workshop, 2008, p.1-2

2008

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Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function

Temperature Dependence of Substrate and Drain-Currents in Bulk FinFETs

The Effect of Adjacent Bit-Line Cell Interference on Random Telegraph Noise in nand Flash Memory Cell Strings

Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)

New Read Schemes Using Boosted Channel Potential of Adjacent Bit-Line Strings in nand Flash Memory

Highly scalable saddle MOSFET for high-density and high-performance DRAM

Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure

Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor

5-bit/cell Characteristics using mixed program/erase mechanism in recessed channel non-volatile memory cells

Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer

Two-Bit/Cell Characteristics of Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Devices with Recessed Channel Structure

Band-to-Band Hot-hole Erase Characteristics of 2-Bit/cell NOR-type Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Cell with Spacer-type Storage Node on Recessed Channel Structure

A new read method suppressing effect of random telegraph noise in NAND flash memory by using hysteretic characteristic

Design of NAND Flash Memory Device by the Fringing Field from a Control Gate

Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors

Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure

Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET

Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias

Dependency of NAND flash memory cells on random dopant fluctuation (RDF) effects

Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

4-bit/cell charge trapping flash device for high density formed in recess region

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