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An analytical timing-driven algorithm for detailed placement

2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 2015, p.1-4

2015

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Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1481-1494

2022

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A low-power configurable VLSI architecture for sum of absolute differences calculation

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 2013, p.1-4

2013

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Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012, p.905-908

2012

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Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012, p.468-471

2012

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Incremental timing optimization for automatic layout generation

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3567-3570 Vol. 4

2005

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VLSI architectures for Digital Modulation Classification using Support Vector Machines

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 2013, p.1-4

2013

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Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 2012, p.1-4

2012

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A high throughput configurable FFT processor for WLAN and WiMax protocols

2012 VIII Southern Conference on Programmable Logic, 2012, p.1-5

2012

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A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design

2011 18th IEEE International Conference on Electronics, Circuits, and Systems, 2011, p.442-445

2011

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Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times

2006 International Caribbean Conference on Devices, Circuits and Systems, 2006, p.345-349

2006

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Soft Error Tolerant Carry-Select Adders Implemented into Altera FPGAs

2007 3rd Southern Conference on Programmable Logic, 2007, p.199-202

2007

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A NOVEL FULL AUTOMATIC LAYOUT GENERATION STRATEGY FOR STATIC CMOS CIRCUITS

VLSI-SOC, 2006, p.197-211

2006

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Improving logic density of QCL masterslices by using universal logic gates

Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216), 1998, p.204-207

1998

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A tool for analysis of universal logic gates functionality

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387), 1999, p.184-187

1999

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An analytical timing-driven algorithm for detailed placement

Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning

A low-power configurable VLSI architecture for sum of absolute differences calculation

Energy-efficient multi-task computing on MPSoCs: A case study from a memory perspective

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

Incremental timing optimization for automatic layout generation

VLSI architectures for Digital Modulation Classification using Support Vector Machines

Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

A high throughput configurable FFT processor for WLAN and WiMax protocols

A1CSA: An energy-efficient fast adder architecture for cell-based VLSI design

Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times

Soft Error Tolerant Carry-Select Adders Implemented into Altera FPGAs

A NOVEL FULL AUTOMATIC LAYOUT GENERATION STRATEGY FOR STATIC CMOS CIRCUITS

Improving logic density of QCL masterslices by using universal logic gates

A tool for analysis of universal logic gates functionality

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