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Incremental timing optimization for automatic layout generation

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3567-3570 Vol. 4

2005

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Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme

48th Midwest Symposium on Circuits and Systems, 2005, 2005, p.315-318 Vol. 1

2005

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Soft Error Tolerant Carry-Select Adders Implemented into Altera FPGAs

2007 3rd Southern Conference on Programmable Logic, 2007, p.199-202

2007

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Mapping Data and Code into Scratchpads from Relocatable Binaries

2009 IEEE Computer Society Annual Symposium on VLSI, 2009, p.157-162

2009

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A transistor sizing method applied to an automatic layout generation tool

16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings, 2003, p.303-307

2003

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Improving critical path identification in functional timing analysis

16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings, 2003, p.297-302

2003

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Finding the critical delay of combinational blocks by floating vector simulation and path tracing

Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 2002, p.277-282

2002

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A novel approach for ASIC layout generation

38th Midwest Symposium on Circuits and Systems. Proceedings, 1995, Vol.2, p.791-794 vol.2

1995

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A tool for analysis of universal logic gates functionality

Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387), 1999, p.184-187

1999

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ATG-based timing analysis of circuits containing complex gates

Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843), 2000, p.21-26

2000

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An improved path enumeration method considering different fall and rise gate delays

Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216), 1998, p.208-211

1998

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Improving logic density of QCL masterslices by using universal logic gates

Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216), 1998, p.204-207

1998

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Incremental timing optimization for automatic layout generation

Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme

Soft Error Tolerant Carry-Select Adders Implemented into Altera FPGAs

Mapping Data and Code into Scratchpads from Relocatable Binaries

A transistor sizing method applied to an automatic layout generation tool

Improving critical path identification in functional timing analysis

Finding the critical delay of combinational blocks by floating vector simulation and path tracing

A novel approach for ASIC layout generation

A tool for analysis of universal logic gates functionality

ATG-based timing analysis of circuits containing complex gates

An improved path enumeration method considering different fall and rise gate delays

Improving logic density of QCL masterslices by using universal logic gates

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