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On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory

IEEE transactions on circuits and systems. I, Regular papers, 2011-02, Vol.58 (2), p.429-439

2011

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Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

IEEE transactions on circuits and systems. I, Regular papers, 2010-10, Vol.57 (10), p.2718-2728

2010

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Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead

IEEE transactions on circuits and systems. I, Regular papers, 2013-09, Vol.60 (9), p.2412-2421

2013

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Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memories

IEEE journal on selected areas in communications, 2014-05, Vol.32 (5), p.880-891

2014

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Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes

IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1350-1354

2013

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Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device

IEEE transactions on very large scale integration (VLSI) systems, 2016-08, Vol.24 (8), p.2654-2664

2016

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Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration

IEEE transactions on very large scale integration (VLSI) systems, 2012-09, Vol.20 (9), p.1705-1714

2012

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Using Lossless Data Compression in Data Storage Systems: Not for Saving Space

IEEE transactions on computers, 2011-03, Vol.60 (3), p.335-345

2011

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Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications

IEEE International Symposium on High-Performance Comp Architecture, 2012, p.1-10

2012

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Techniques Mitigating Update-Induced Latency Overhead in Shingled Magnetic Recording

IEEE transactions on magnetics, 2012-05, Vol.48 (5), p.1899-1905

2012

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Using Quasi-EZ-NAND Flash Memory to Build Large-Capacity Solid-State Drives in Computing Systems

IEEE transactions on computers, 2013-05, Vol.62 (5), p.1051-1057

2013

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Joint Source-Channel Coding and Channelization for Embedded Video Processing With Flash Memory Storage

IEEE transactions on signal processing, 2012-08, Vol.60 (8), p.4403-4414

2012

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Reducing Read Latency of Shingled Magnetic Recording With Severe Intertrack Interference Using Transparent Lossless Data Compression

IEEE transactions on magnetics, 2013-08, Vol.49 (8), p.4761-4767

2013

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Reducing data transfer latency of NAND flash memory with soft-decision sensing

2012 IEEE International Conference on Communications (ICC), 2012, p.7024-7028

2012

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Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance

IEEE transactions on very large scale integration (VLSI) systems, 2014-06, Vol.22 (6), p.1270-1280

2014

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Reducing latency overhead caused by using LDPC codes in NAND flash memory

EURASIP journal on advances in signal processing, 2012-09, Vol.2012 (1), p.1-9, Article 203

2012

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On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory

Circuits, systems, and signal processing, 2015-02, Vol.34 (2), p.557-577

2015

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Reducing latency overhead caused by using LDPC codes in NAND flash memory: Doc 304

EURASIP journal on advances in signal processing, 2012-09, Vol.2012, p.1

2012

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Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory

2014 30th Symposium on Mass Storage Systems and Technologies (MSST), 2014, p.1-6

2014

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Hybrid hard-/soft-decision LDPC decoding strategy for NAND flash memory

Chinese science bulletin, 2014-10, Vol.59 (28), p.3554-3561

2014

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A First Study on Self-Healing Solid-State Drives

2011 3rd IEEE International Memory Workshop (IMW), 2011, p.1-4

2011

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High performance NAND flash memory system design

Dong, Guiqiang

2012

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Techniques for embracing intra-cell unbalanced bit error characteristics in MLC NAND flash memory

2010 IEEE Globecom Workshops, 2010, p.1915-1920

2010

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Applying transparent lossless data compression to improve the feasibility of using advanced error correction codes in solid-state drives

2010 IEEE Workshop On Signal Processing Systems, 2010, p.31-35

2010

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Candidate bit based bit-flipping decoding algorithm for LDPC codes

2009 IEEE International Symposium on Information Theory, 2009, p.2166-2168

2009

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On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory

Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead

Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memories

Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes

Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device

Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration

Using Lossless Data Compression in Data Storage Systems: Not for Saving Space

Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications

Techniques Mitigating Update-Induced Latency Overhead in Shingled Magnetic Recording

Using Quasi-EZ-NAND Flash Memory to Build Large-Capacity Solid-State Drives in Computing Systems

Joint Source-Channel Coding and Channelization for Embedded Video Processing With Flash Memory Storage

Reducing Read Latency of Shingled Magnetic Recording With Severe Intertrack Interference Using Transparent Lossless Data Compression

Reducing data transfer latency of NAND flash memory with soft-decision sensing

Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance

Reducing latency overhead caused by using LDPC codes in NAND flash memory

On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory

Reducing latency overhead caused by using LDPC codes in NAND flash memory: Doc 304

Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory

Hybrid hard-/soft-decision LDPC decoding strategy for NAND flash memory

A First Study on Self-Healing Solid-State Drives

High performance NAND flash memory system design

Techniques for embracing intra-cell unbalanced bit error characteristics in MLC NAND flash memory

Applying transparent lossless data compression to improve the feasibility of using advanced error correction codes in solid-state drives

Candidate bit based bit-flipping decoding algorithm for LDPC codes

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