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DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications

IEEE journal of solid-state circuits, 2018-09, Vol.53 (9), p.2722-2731

2018

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A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.206-219

2012

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MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance

IEEE MICRO, 2020-03, Vol.40 (2), p.8-16

2020

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A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs

IEEE journal of solid-state circuits, 2019-07, Vol.54 (7), p.1982-1992

2019

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Chasing Carbon: The Elusive Environmental Footprint of Computing

IEEE MICRO, 2022-07, Vol.42 (4), p.37-47

2022

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Profiling a warehouse-scale computer

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.158-169

2015

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A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications

IEEE journal of solid-state circuits, 2016-09, Vol.51 (9), p.2142-2152

2016

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A Low Mass Power Electronics Unit to Drive Piezoelectric Actuators for Flying Microrobots

IEEE transactions on power electronics, 2018-04, Vol.33 (4), p.3180-3191

2018

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MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge

IEEE MICRO, 2019-11, Vol.39 (6), p.73-81

2019

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Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-04, Vol.43 (4), p.1037-1050

2024

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A Binary-activation, Multi-level Weight RNN and Training Algorithm for ADC-/DAC-free and Noise-resilient Processing-in-memory Inference with eNVM

IEEE transactions on emerging topics in computing, 2023-04, Vol.11 (2), p.1-11

2023

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End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators

IEEE transactions on computers, 2022-12, Vol.71 (12), p.3074-3087

2022

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Architectural CO2 Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool

IEEE MICRO, 2023-07, Vol.43 (4), p.107

2023

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Bridging Python to Silicon: The SODA Toolchain

IEEE MICRO, 2022-09, Vol.42 (5), p.78-88

2022

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A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs

IEEE journal of solid-state circuits, 2023-02, Vol.58 (2), p.569-581

2023

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A case for efficient accelerator design space exploration via Bayesian optimization

2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2017, p.1-6

2017

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An Area-Efficient 8-Bit Single-Ended ADC With Extended Input Voltage Range

IEEE transactions on circuits and systems. II, Express briefs, 2018-11, Vol.65 (11), p.1549-1553

2018

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The Aladdin Approach to Accelerator Design and Modeling

IEEE MICRO, 2015-05, Vol.35 (3), p.58-70

2015

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The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines

IEEE computer architecture letters, 2020-01, Vol.19 (1), p.38-42

2020

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CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development

IEEE MICRO, 2020-07, Vol.40 (4), p.32-40

2020

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Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis

IEEE transactions on circuits and systems. II, Express briefs, 2018-10, Vol.65 (10), p.1440-1444

2018

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A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1271-1284

2017

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Co-designing accelerators and SoC interfaces using gem5-Aladdin

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2016, p.1-12

2016

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Predicting New Workload or CPU Performance by Analyzing Public Datasets

ACM transactions on architecture and code optimization, 2019-01, Vol.15 (4), p.1-21

2019

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CAMEL: Co-Designing AI Models and eDRAMs for Efficient On-Device Learning

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.861-875

2024

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DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications

A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS

MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance

A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs

Chasing Carbon: The Elusive Environmental Footprint of Computing

Profiling a warehouse-scale computer

A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications

A Low Mass Power Electronics Unit to Drive Piezoelectric Actuators for Flying Microrobots

MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge

Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs

A Binary-activation, Multi-level Weight RNN and Training Algorithm for ADC-/DAC-free and Noise-resilient Processing-in-memory Inference with eNVM

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators

Architectural CO2 Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool

Bridging Python to Silicon: The SODA Toolchain

A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs

A case for efficient accelerator design space exploration via Bayesian optimization

An Area-Efficient 8-Bit Single-Ended ADC With Extended Input Voltage Range

The Aladdin Approach to Accelerator Design and Modeling

The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines

CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development

Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis

A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter

Co-designing accelerators and SoC interfaces using gem5-Aladdin

Predicting New Workload or CPU Performance by Analyzing Public Datasets

CAMEL: Co-Designing AI Models and eDRAMs for Efficient On-Device Learning

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