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Timing analysis for full-custom circuits using symbolic DC formulations

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-09, Vol.25 (9), p.1815-1830

2006

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A 1.2GHz alpha microprocessor with 44.8GB/s chip pin bandwidth

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2001

2001

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Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-04, Vol.24 (4), p.502-515

2005

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Logic decomposition during technology mapping

IEEE transactions on computer-aided design of integrated circuits and systems, 1997-08, Vol.16 (8), p.813-834

1997

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A low-cost, 300-MHz, RISC CPU with attached media processor

IEEE journal of solid-state circuits, 1998-11, Vol.33 (11), p.1829-1839

1998

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Automatic generation of critical-path tests for a partial-scan microprocessor

Proceedings 21st International Conference on Computer Design, 2003, p.180-186

2003

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AutoRex: An automated post-silicon clock tuning tool

2009 International Test Conference, 2009, p.1-10

2009

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Symbolic failure analysis of custom circuits due to excessive leakage current

Proceedings 21st International Conference on Computer Design, 2003, p.70-75

2003

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Static race verification for networks with reconvergent clocks

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273), 1998, p.524-529

1998

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Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-6

2007

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Accurate timing analysis using SAT and pattern-dependent delay models

Proceedings of the conference on Design, automation and test in Europe, 2007, p.1018-1023

2007

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Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation

26th IEEE VLSI Test Symposium (vts 2008), 2008, p.339-344

2008

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A simple algorithm for fanout optimization using high-performance buffer libraries

Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, 1993, p.466-471

1993

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Race detection for two-phase systems

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1990, p.20-23

1990

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Timing verification on a 1.2M-device full-custom CMOS design

28th ACM/IEEE Design Automation Conference, 1991, p.551-554

1991

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Accurate timing analysis using SAT and pattern-dependent delay models

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 16-20 Apr. 2007, 2007, p.1018-1023

2007

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A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.240-241

2001

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A low-cost 300 MHz RISC CPU with attached media processor

1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156), 1998, p.298-299

1998

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Logic decomposition during technology mapping

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995, p.264-271

1995

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A delay model for logic synthesis of continuously-sized networks

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995, p.458-462

1995

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Logic decomposition during technology mapping

Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, 1995, p.264-271

1995

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A delay model for logic synthesis of continuously-sized networks

Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, 1995, p.458-462

1995

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Optimal Latch Mapping And Retiming Within A Tree

IEEE/ACM International Conference on Computer-Aided Design, 1994, p.242-245

1994

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A simple algorithm for fanout optimization using high-performance buffer libraries

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993, p.466-471

1993

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System, process, and design implications of a reduced supply voltage microprocessor

1990 37th IEEE International Conference on Solid-State Circuits, 1990, p.48-49

1990

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Timing analysis for full-custom circuits using symbolic DC formulations

A 1.2GHz alpha microprocessor with 44.8GB/s chip pin bandwidth

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing

Logic decomposition during technology mapping

A low-cost, 300-MHz, RISC CPU with attached media processor

Automatic generation of critical-path tests for a partial-scan microprocessor

AutoRex: An automated post-silicon clock tuning tool

Symbolic failure analysis of custom circuits due to excessive leakage current

Static race verification for networks with reconvergent clocks

Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models

Accurate timing analysis using SAT and pattern-dependent delay models

Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation

A simple algorithm for fanout optimization using high-performance buffer libraries

Race detection for two-phase systems

Timing verification on a 1.2M-device full-custom CMOS design

Accurate timing analysis using SAT and pattern-dependent delay models

A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth

A low-cost 300 MHz RISC CPU with attached media processor

Logic decomposition during technology mapping

A delay model for logic synthesis of continuously-sized networks

Logic decomposition during technology mapping

A delay model for logic synthesis of continuously-sized networks

Optimal Latch Mapping And Retiming Within A Tree

A simple algorithm for fanout optimization using high-performance buffer libraries

System, process, and design implications of a reduced supply voltage microprocessor

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