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On design and implementation of a decimation filter for multistandard wireless transceivers

IEEE transactions on wireless communications, 2002-10, Vol.1 (4), p.558-562

2002

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An Efficient Flexible Common Operator for FFT and Viterbi Algorithms

2011 IEEE 73rd Vehicular Technology Conference (VTC Spring), 2011, p.1-5

2011

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Cognitive engine design for cognitive radio

2012 International Conference on Multimedia Computing and Systems, 2012, p.986-991

2012

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High level design flow targeting real multistandard circuit designer requirements

Journal of communication and computer, 2011-01, Vol.1 (7), p.ISSN 1548-7709

2011

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High Level Design Flow Targeting Real Multistandard Circuit Designer Requirements

Journal of communication and computer, 2011-05, Vol.8 (5), p.335-346

2011

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Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

2009 IEEE Wireless Communications and Networking Conference, 2009, p.1-6

2009

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Design of down-sampling processors for radio communications

Analog integrated circuits and signal processing, 2003-07, Vol.36 (1-2), p.31-38

2003

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Design and hardware implementation of digital channel selection processor for radio receiver

Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, 2004, 2004, p.152-156

2004

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Optimized FPGA-based implementation of down-sampling filter for wide band radio receiver

2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04, 2004, Vol.1, p.243-245 Vol. 1

2004

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Relaxed decimation filter specifications for wireless transceivers

9th International Conference on Electronics, Circuits and Systems, 2002, Vol.2, p.565-569 vol.2

2002

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Design and implementation of cascade decimation filter for radio communications

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2001, Vol.3, p.1603-1606 vol.3

2001

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A flexible processor for FFT and Viterbi algorithms

2012 International Symposium on Communications and Information Technologies (ISCIT), 2012, p.931-935

2012

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Statistical decision making method for cognitive radio

2012 19th International Conference on Telecommunications (ICT), 2012, p.1-6

2012

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Power consumption estimation models for FIR decimation filters in multi-standard receivers

2011 IEEE GCC Conference and Exhibition (GCC), 2011, p.617-620

2011

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Software embedded implementation of real time non uniform sampling filter

2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, 2009, p.86-89

2009

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Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing

2008 2nd International Conference on Signals, Circuits and Systems, 2008, p.1-6

2008

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Design and hardware implementation of digital channel selection decimating filter for multistandard receiver

2005 12th IEEE International Conference on Electronics, Circuits and Systems, 2005, p.1-4

2005

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Evaluation of FIR filters implementations for low power multistandard receivers

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2010, p.1-5

2010

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Software efficient implementation of GMSK modem for an automatic identification system transceiver

2008 Canadian Conference on Electrical and Computer Engineering, 2008, p.000601-000606

2008

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Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.1183-1186

2007

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Low power FPGA-based implementation of decimating filters for multistandard receiver

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006, 2006, p.10-14

2006

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Low Power Design of a Decimation Filter in Multi-Standard Receiver

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008, p.1-5

2008

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Design and Implementation of AIS Link Layer Using SDL-RT

2008 2nd Annual IEEE Systems Conference, 2008, p.1-5

2008

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Non-Uniform Sampled Signal Reconstruction for Multistandard WiMAX/WiFi Receiver

2007 IEEE International Conference on Signal Processing and Communications, 2007, p.181-184

2007

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FPGA bulding blocks for an hybrid base band digital predistorter suitable for 3G power\amplifiers

2005 12th IEEE International Conference on Electronics, Circuits and Systems, 2005, p.1-4

2005

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On design and implementation of a decimation filter for multistandard wireless transceivers

An Efficient Flexible Common Operator for FFT and Viterbi Algorithms

Cognitive engine design for cognitive radio

High level design flow targeting real multistandard circuit designer requirements

High Level Design Flow Targeting Real Multistandard Circuit Designer Requirements

Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

Design of down-sampling processors for radio communications

Design and hardware implementation of digital channel selection processor for radio receiver

Optimized FPGA-based implementation of down-sampling filter for wide band radio receiver

Relaxed decimation filter specifications for wireless transceivers

Design and implementation of cascade decimation filter for radio communications

A flexible processor for FFT and Viterbi algorithms

Statistical decision making method for cognitive radio

Power consumption estimation models for FIR decimation filters in multi-standard receivers

Software embedded implementation of real time non uniform sampling filter

Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing

Design and hardware implementation of digital channel selection decimating filter for multistandard receiver

Evaluation of FIR filters implementations for low power multistandard receivers

Software efficient implementation of GMSK modem for an automatic identification system transceiver

Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

Low power FPGA-based implementation of decimating filters for multistandard receiver

Low Power Design of a Decimation Filter in Multi-Standard Receiver

Design and Implementation of AIS Link Layer Using SDL-RT

Non-Uniform Sampled Signal Reconstruction for Multistandard WiMAX/WiFi Receiver

FPGA bulding blocks for an hybrid base band digital predistorter suitable for 3G power\amplifiers

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