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UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications

IEEE transactions on circuits and systems. II, Express briefs, 2016-10, Vol.63 (10), p.994-998

2016

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Activation Function Integration for Accelerating Multi-Layer Graph Convolutional Neural Networks

17TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE, DCAS 2024, 2024, p.1-6

2024

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Improved Range Analysis in Fixed-Point Polynomial Data-Path

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-11, Vol.36 (11), p.1925-1929

2017

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Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.398-402

2016

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Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training

APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2024, 2024, p.33-47

2024

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Cell design methodology (CDM) for balanced Carry-InverseCarry circuits in hybrid-CMOS logic style

International journal of electronics, 2014-10, Vol.101 (10), p.1357-1374

2014

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Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style

Journal of low-power electronics, 2010-12, Vol.6 (4), p.503-512

2010

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Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks

2022 23rd International Symposium on Quality Electronic Design (ISQED), 2022, p.1-6

2022

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ACPA: Exploiting Approximate Computing for High-Level Imprecision Optimization of Fixed-point LTI systems

2020 IEEE 14th Dallas Circuits and Systems Conference (DCAS), 2020, p.1-6

2020

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Hardware-assisted Neural Network IP Protection using Non-malicious Backdoor and Selective Weight Obfuscation

2022 IEEE 15th Dallas Circuit And System Conference (DCAS), 2022, p.1-6

2022

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CNTFET full-adders for energy-efficient arithmetic applications

2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2015, p.1-6

2015

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Cell design methodology for balanced carry-carrybar circuits in hybrid-CMOS logic style

2011 10th International Workshop on Electronics, Control, Measurement and Signals, 2011, p.1-5

2011

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Design of a 10-nm FinFET 11 T Near-Threshold SRAM Cell for Low-Energy Internet-of-Things Applications

Circuits, systems, and signal processing, 2023-05, Vol.42 (5), p.3138-3151

2023

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UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications

Activation Function Integration for Accelerating Multi-Layer Graph Convolutional Neural Networks

Improved Range Analysis in Fixed-Point Polynomial Data-Path

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training

Cell design methodology (CDM) for balanced Carry-InverseCarry circuits in hybrid-CMOS logic style

Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style

Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks

ACPA: Exploiting Approximate Computing for High-Level Imprecision Optimization of Fixed-point LTI systems

Hardware-assisted Neural Network IP Protection using Non-malicious Backdoor and Selective Weight Obfuscation

CNTFET full-adders for energy-efficient arithmetic applications

Cell design methodology for balanced carry-carrybar circuits in hybrid-CMOS logic style

Design of a 10-nm FinFET 11 T Near-Threshold SRAM Cell for Low-Energy Internet-of-Things Applications

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