UB Paderborn / Katalog / Suche / in CDI

Evaluation of design alternatives for the 2-D-discrete wavelet transform

IEEE transactions on circuits and systems for video technology, 2001-12, Vol.11 (12), p.1246-1262

2001

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A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores

IEEE transactions on dependable and secure computing, 2009-10, Vol.6 (4), p.255-268

2009

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A high-performance data path for synthesizing DSP kernels

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1154-1162

2006

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Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

IEEE transactions on very large scale integration (VLSI) systems, 2007-12, Vol.15 (12), p.1362-1366

2007

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Memory accesses reordering for interconnect power reduction in sum-of-products computations

IEEE transactions on signal processing, 2002-11, Vol.50 (11), p.2889-2899

2002

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Maximizing the hash function of authentication codes

IEEE potentials, 2006-03, Vol.25 (2), p.9-12

2006

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Power efficient data path synthesis of sum-of-products computations

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.446-450

2003

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Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Field Programmable Logic and Application, 2004, p.868-873

2004

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A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Integration (Amsterdam), 2005-09, Vol.39 (1), p.1-11

2005

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A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

IEEE transactions on very large scale integration (VLSI) systems, 2002-08, Vol.10 (4), p.515-518

2002

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Performance improvements from partitioning applications to FPGA hardware in embedded SoCs

The Journal of supercomputing, 2006-02, Vol.35 (2), p.185-199

2006

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A Novel Data-Path for Accelerating DSP Kernels

Computer Systems: Architectures, Modeling, and Simulation, 2004, p.363-372

2004

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A low-power and high-throughput implementation of the SHA-1 hash function

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.4086-4089 Vol. 4

2005

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Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.492-497

1999

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A novel algorithm for low-power image and video coding

IEEE transactions on circuits and systems for video technology, 1998-06, Vol.8 (3), p.258-263

1998

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A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

Design, Automation and Test in Europe, 2005, p.247-252

2005

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Low-power design of direct conversion baseband DECT receiver

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2001-12, Vol.48 (12), p.1121-1131

2001

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Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: A pre-compiler for multimedia applications

Design automation for embedded systems, 2003-03, Vol.8 (1), p.51-86

2003

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An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3519-3522 Vol. 4

2005

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A code transformation-based methodology for improving I-cache performance of DSP applications

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.977-983

2002

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A methodology for partitioning DSP applications in hybrid reconfigurable systems

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.1206-1209 Vol. 2

2005

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Improved switched-current (SI) bilinear integrator circuit

Electronics letters, 1995-01, Vol.31 (1), p.26-27

1995

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Power Efficient Hierarchical Scheduling for DSP Transformations

VLSI Design, 2002, Vol.2002 (2), p.203-217

2002

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Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores

VLSI Design, 2002, Vol.2002 (3), p.273-286

2002

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Low power architectures for digital signal processing

Journal of systems architecture, 2000-04, Vol.46 (7), p.551-571

2000

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Evaluation of design alternatives for the 2-D-discrete wavelet transform

A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores

A high-performance data path for synthesizing DSP kernels

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

Memory accesses reordering for interconnect power reduction in sum-of-products computations

Maximizing the hash function of authentication codes

Power efficient data path synthesis of sum-of-products computations

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

Performance improvements from partitioning applications to FPGA hardware in embedded SoCs

A Novel Data-Path for Accelerating DSP Kernels

A low-power and high-throughput implementation of the SHA-1 hash function

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

A novel algorithm for low-power image and video coding

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

Low-power design of direct conversion baseband DECT receiver

Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: A pre-compiler for multimedia applications

An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays

A code transformation-based methodology for improving I-cache performance of DSP applications

A methodology for partitioning DSP applications in hybrid reconfigurable systems

Improved switched-current (SI) bilinear integrator circuit

Power Efficient Hierarchical Scheduling for DSP Transformations

Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores

Low power architectures for digital signal processing

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