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Evaluation of design alternatives for the 2-D-discrete wavelet transform

IEEE transactions on circuits and systems for video technology, 2001-12, Vol.11 (12), p.1246-1262

2001

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A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores

IEEE transactions on dependable and secure computing, 2009-10, Vol.6 (4), p.255-268

2009

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A high-performance data path for synthesizing DSP kernels

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1154-1162

2006

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Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

IEEE transactions on very large scale integration (VLSI) systems, 2007-12, Vol.15 (12), p.1362-1366

2007

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Maximizing the hash function of authentication codes

IEEE potentials, 2006-03, Vol.25 (2), p.9-12

2006

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Memory accesses reordering for interconnect power reduction in sum-of-products computations

IEEE transactions on signal processing, 2002-11, Vol.50 (11), p.2889-2899

2002

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Power efficient data path synthesis of sum-of-products computations

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.446-450

2003

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A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

IEEE transactions on very large scale integration (VLSI) systems, 2002-08, Vol.10 (4), p.515-518

2002

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A low-power and high-throughput implementation of the SHA-1 hash function

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.4086-4089 Vol. 4

2005

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On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

Integration (Amsterdam), 2014, Vol.47 (4), p.387-407

2014

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Low-power design of direct conversion baseband DECT receiver

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2001-12, Vol.48 (12), p.1121-1131

2001

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Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

IET computers & digital techniques, 2009, Vol.3 (1), p.109-123

2009

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A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Integration (Amsterdam), 2005-09, Vol.39 (1), p.1-11

2005

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Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Microprocessors and microsystems, 2007-02, Vol.31 (1), p.1-14

2007

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Resource constrained modulo scheduling for coarse-grained reconfigurable arrays

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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Implementation of HSSec: a High-Speed Cryptographic Co-Processor

2007 IEEE Conference on Emerging Technologies and Factory Automation (EFTA 2007), 2007, p.625-631

2007

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A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-6

2007

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Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.492-497

1999

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A wavelet-tree image coding system with efficient memory utilization

2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), 2001, Vol.3, p.1709-1712 vol.3

2001

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A novel algorithm for low-power image and video coding

IEEE transactions on circuits and systems for video technology, 1998-06, Vol.8 (3), p.258-263

1998

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A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

Design, Automation and Test in Europe, 2005, p.247-252

2005

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A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.472-475 Vol. 1

2005

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Quantization effect on VLSI implementations for the 9/7 DWT filters

2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), 2001, Vol.2, p.1197-1200 vol.2

2001

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An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3519-3522 Vol. 4

2005

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Evaluation of design alternatives for the 2-D-discrete wavelet transform

A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores

A high-performance data path for synthesizing DSP kernels

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

Maximizing the hash function of authentication codes

Memory accesses reordering for interconnect power reduction in sum-of-products computations

Power efficient data path synthesis of sum-of-products computations

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

A low-power and high-throughput implementation of the SHA-1 hash function

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

Low-power design of direct conversion baseband DECT receiver

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Resource constrained modulo scheduling for coarse-grained reconfigurable arrays

Mapping DSP applications on processor/coarse-grain reconfigurable array architectures

Implementation of HSSec: a High-Speed Cryptographic Co-Processor

A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

A wavelet-tree image coding system with efficient memory utilization

A novel algorithm for low-power image and video coding

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard

Quantization effect on VLSI implementations for the 9/7 DWT filters

An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays

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