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On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

Integration (Amsterdam), 2014, Vol.47 (4), p.387-407

2014

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Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

IET computers & digital techniques, 2009, Vol.3 (1), p.109-123

2009

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A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Integration (Amsterdam), 2005-09, Vol.39 (1), p.1-11

2005

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Evaluation of design alternatives for the 2-D-discrete wavelet transform

IEEE transactions on circuits and systems for video technology, 2001-12, Vol.11 (12), p.1246-1262

2001

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Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Field Programmable Logic and Application, 2004, p.868-873

2004

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A high-performance data path for synthesizing DSP kernels

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1154-1162

2006

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A novel algorithm for low-power image and video coding

IEEE transactions on circuits and systems for video technology, 1998-06, Vol.8 (3), p.258-263

1998

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Novel Hardware Implementation of the Cipher Message Authentication Code

Journal of computer networks and communications, 2008-01, Vol.2008 (1)

2008

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Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

IEEE transactions on very large scale integration (VLSI) systems, 2007-12, Vol.15 (12), p.1362-1366

2007

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A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

Design, Automation and Test in Europe, 2005, p.247-252

2005

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Improved switched-current (SI) bilinear integrator circuit

Electronics letters, 1995-01, Vol.31 (1), p.26-27

1995

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Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: A pre-compiler for multimedia applications

Design automation for embedded systems, 2003-03, Vol.8 (1), p.51-86

2003

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A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

IEEE transactions on signal processing, 2011-12, Vol.59 (12), p.6217-6226

2011

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Memory accesses reordering for interconnect power reduction in sum-of-products computations

IEEE transactions on signal processing, 2002-11, Vol.50 (11), p.2889-2899

2002

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Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Microprocessors and microsystems, 2007-02, Vol.31 (1), p.1-14

2007

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Power Efficient Hierarchical Scheduling for DSP Transformations

VLSI Design, 2002, Vol.2002 (2), p.203-217

2002

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Maximizing the hash function of authentication codes

IEEE potentials, 2006-03, Vol.25 (2), p.9-12

2006

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Power efficient data path synthesis of sum-of-products computations

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.446-450

2003

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Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores

VLSI Design, 2002, Vol.2002 (3), p.273-286

2002

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A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

IEEE transactions on very large scale integration (VLSI) systems, 2002-08, Vol.10 (4), p.515-518

2002

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A systematic methodology for mapping DSP algorithms onto multilevel array architectures

International journal of electronics, 1995-11, Vol.79 (5), p.507-518

1995

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Image reconstruction on a special purpose array processor

Image and vision computing, 1992, Vol.10 (7), p.479-484, Article 479

1992

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Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

VLSI Design, 1999-01, Vol.1998 (2), p.177-202

1999

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Array processor for block adaptive LS FIR filtering

Signal processing, 1994, Vol.39 (1), p.215-222

1994

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A RECONFIGURABLE COARSE-GRAIN DATA-PATH FOR ACCELERATING COMPUTATIONAL INTENSIVE KERNELS

Journal of circuits, systems, and computers, 2005-08, Vol.14 (4), p.877-893

2005

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On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Evaluation of design alternatives for the 2-D-discrete wavelet transform

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

A high-performance data path for synthesizing DSP kernels

A novel algorithm for low-power image and video coding

Novel Hardware Implementation of the Cipher Message Authentication Code

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

Improved switched-current (SI) bilinear integrator circuit

Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: A pre-compiler for multimedia applications

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

Memory accesses reordering for interconnect power reduction in sum-of-products computations

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Power Efficient Hierarchical Scheduling for DSP Transformations

Maximizing the hash function of authentication codes

Power efficient data path synthesis of sum-of-products computations

Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

A systematic methodology for mapping DSP algorithms onto multilevel array architectures

Image reconstruction on a special purpose array processor

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis

Array processor for block adaptive LS FIR filtering

A RECONFIGURABLE COARSE-GRAIN DATA-PATH FOR ACCELERATING COMPUTATIONAL INTENSIVE KERNELS

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