UB Paderborn / Katalog / Suche / in CDI

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

Integration (Amsterdam), 2014, Vol.47 (4), p.387-407

2014

Link zum Volltext

Verfügbarkeit prüfen

Evaluation of design alternatives for the 2-D-discrete wavelet transform

IEEE transactions on circuits and systems for video technology, 2001-12, Vol.11 (12), p.1246-1262

2001

Link zum Volltext
IEEE_Xplore

A high-performance data path for synthesizing DSP kernels

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1154-1162

2006

Link zum Volltext
IEEE_Xplore

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

IET computers & digital techniques, 2009, Vol.3 (1), p.109-123

2009

Link zum Volltext

Verfügbarkeit prüfen

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

IEEE transactions on very large scale integration (VLSI) systems, 2007-12, Vol.15 (12), p.1362-1366

2007

Link zum Volltext
IEEE_Xplore

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Integration (Amsterdam), 2005-09, Vol.39 (1), p.1-11

2005

Link zum Volltext

Verfügbarkeit prüfen

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Field Programmable Logic and Application, 2004, p.868-873

2004

Link zum Volltext

Verfügbarkeit prüfen

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.492-497

1999

Link zum Volltext
IEEE_Xplore

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

IEEE transactions on signal processing, 2011-12, Vol.59 (12), p.6217-6226

2011

Link zum Volltext
IEEE_Xplore

A novel algorithm for low-power image and video coding

IEEE transactions on circuits and systems for video technology, 1998-06, Vol.8 (3), p.258-263

1998

Link zum Volltext
IEEE_Xplore

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Microprocessors and microsystems, 2007-02, Vol.31 (1), p.1-14

2007

Link zum Volltext

Verfügbarkeit prüfen

Memory accesses reordering for interconnect power reduction in sum-of-products computations

IEEE transactions on signal processing, 2002-11, Vol.50 (11), p.2889-2899

2002

Link zum Volltext
IEEE_Xplore

Novel Hardware Implementation of the Cipher Message Authentication Code

Journal of computer networks and communications, 2008-01, Vol.2008 (1)

2008

Link zum Volltext

Verfügbarkeit prüfen

Explaining the Saddlepoint Approximation

The American statistician, 1999-08, Vol.53 (3), p.216-224

1999

Link zum Volltext

Verfügbarkeit prüfen

Maximizing the hash function of authentication codes

IEEE potentials, 2006-03, Vol.25 (2), p.9-12

2006

Link zum Volltext
IEEE_Xplore

Power efficient data path synthesis of sum-of-products computations

IEEE transactions on very large scale integration (VLSI) systems, 2003-06, Vol.11 (3), p.446-450

2003

Link zum Volltext
IEEE_Xplore

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

Design, Automation and Test in Europe, 2005, p.247-252

2005

Link zum Volltext
IEEE_Xplore

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

IEEE transactions on very large scale integration (VLSI) systems, 2002-08, Vol.10 (4), p.515-518

2002

Link zum Volltext
IEEE_Xplore

Explaining the Saddlepoint Approximation

The American statistician, 1999-08, Vol.53 (3), p.216

1999

Link zum Volltext

Verfügbarkeit prüfen

Improved switched-current (SI) bilinear integrator circuit

Electronics letters, 1995-01, Vol.31 (1), p.26-27

1995

Link zum Volltext

Verfügbarkeit prüfen

Strategy for power-efficient design of parallel systems

IEEE transactions on very large scale integration (VLSI) systems, 1999-06, Vol.7 (2), p.258-265

1999

Link zum Volltext
IEEE_Xplore

Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: A pre-compiler for multimedia applications

Design automation for embedded systems, 2003-03, Vol.8 (1), p.51-86

2003

Link zum Volltext

Verfügbarkeit prüfen

A code transformation-based methodology for improving I-cache performance of DSP applications

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.977-983

2002

Link zum Volltext
IEEE_Xplore

Partial Least Squares Algorithm Yields Shrinkage Estimators

The Annals of statistics, 1996-04, Vol.24 (2), p.816-824

Goutis, Constantinos

1996

Link zum Volltext

Verfügbarkeit prüfen

Power Efficient Hierarchical Scheduling for DSP Transformations

VLSI Design, 2002, Vol.2002 (2), p.203-217

2002

Link zum Volltext

Verfügbarkeit prüfen

Menü

Weitere Dienste

Einstellungen

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

Evaluation of design alternatives for the 2-D-discrete wavelet transform

A high-performance data path for synthesizing DSP kernels

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

A novel algorithm for low-power image and video coding

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms

Memory accesses reordering for interconnect power reduction in sum-of-products computations

Novel Hardware Implementation of the Cipher Message Authentication Code

Explaining the Saddlepoint Approximation

Maximizing the hash function of authentication codes

Power efficient data path synthesis of sum-of-products computations

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

Explaining the Saddlepoint Approximation

Improved switched-current (SI) bilinear integrator circuit

Strategy for power-efficient design of parallel systems

Systematic application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in ACROPOLIS: A pre-compiler for multimedia applications

A code transformation-based methodology for improving I-cache performance of DSP applications

Partial Least Squares Algorithm Yields Shrinkage Estimators

Power Efficient Hierarchical Scheduling for DSP Transformations

Suchergebnisse filtern