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System Level ESD Co-Design

1st ed., 2015

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Physics of Current Filamentation in ggNMOS Devices Under ESD Condition Revisited

IEEE transactions on electron devices, 2018-07, Vol.65 (7), p.2981-2989

2018

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IEEE_Xplore

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

IEEE transactions on electron devices, 2012-05, Vol.59 (5), p.1353-1363

2012

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IEEE_Xplore

On the Electrostatic Discharge Robustness of Graphene

IEEE transactions on electron devices, 2014-06, Vol.61 (6), p.1920-1928

2014

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IEEE_Xplore

Simulation Methods for ESD Protection Development

1, 2003

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Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, p.391-394

2017

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IEEE_Xplore

Tunnel-field-effect-transistor based gas-sensor: Introducing gas detection with a quantum-mechanical transducer

Applied physics letters, 2013-01, Vol.102 (2)

2013

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An Island Drain Double-Gate DeMOS With Self-Aligned Sub-Gate to Achieve Multifold Transient Frequency Enhancement

IEEE transactions on electron devices, 2022-09, Vol.69 (9), p.5074-5081

2022

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IEEE_Xplore

Physical Insights Into the ESD Behavior of Drain Extended FinFETs (DeFinFETs) and Unique Current Filament Dynamics

IEEE transactions on electron devices, 2020-07, Vol.67 (7), p.2717-2724

2020

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IEEE_Xplore

Modular Measurement System for System-Efficient ESD Design on System and Component Level

IEEE transactions on electromagnetic compatibility, 2022-12, Vol.64 (6), p.1-8

2022

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IEEE_Xplore

Reliability aspects of gate oxide under ESD pulse stress

Microelectronics and reliability, 2009-12, Vol.49 (12), p.1407-1416

2009

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Design for ESD protection at its limits

2013 Symposium on VLSI Technology, 2013, p.T120-T121

Gossner, Harald

2013

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IEEE_Xplore

Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications

IEEE transactions on electron devices, 2020-11, Vol.67 (11), p.4728-4735

2020

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IEEE_Xplore

Impact-ionization field-effect-transistor based biosensors for ultra-sensitive detection of biomolecules

Applied physics letters, 2013-05, Vol.102 (20)

2013

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IC Pin Modeling and Mitigation of ESD-Induced Soft Failures

IEEE transactions on electromagnetic compatibility, 2021-04, Vol.63 (2), p.375-383

2021

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IEEE_Xplore

A Tunnel FET for V DD Scaling Below 0.6 V With a CMOS-Comparable Performance

IEEE transactions on electron devices, 2011-07, Vol.58 (7), p.1855-1863

2011

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A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance

IEEE transactions on electron devices, 2011-07, Vol.58 (7), p.1855-1863

2011

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Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability

IEEE transactions on electron devices, 2020-07, Vol.67 (7), p.2745-2751

2020

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IEEE_Xplore

Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs

IEEE transactions on electron devices, 2019-12, Vol.66 (12), p.5072-5079

2019

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IEEE_Xplore

A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge

IEEE transactions on electromagnetic compatibility, 2020-02, Vol.62 (1), p.16-24

2020

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IEEE_Xplore

Challenges & Physical Insights Into the Design of Fin-Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection

IEEE transactions on electron devices, 2018-11, Vol.65 (11), p.4755-4763

2018

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IEEE_Xplore

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

IEEE transactions on electron devices, 2011-04, Vol.58 (4), p.1045-1053

2011

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IEEE_Xplore

Advanced simulation methods for ESD protection development

2003

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Identification of Soft Failure Mechanisms Triggered by ESD Stress on a Powered USB 3.0 Interface

IEEE transactions on electromagnetic compatibility, 2019-02, Vol.61 (1), p.20-28

2019

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IEEE_Xplore

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

IEEE transactions on electron devices, 2015-10, Vol.62 (10), p.3168-3175

2015

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IEEE_Xplore

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System Level ESD Co-Design

Physics of Current Filamentation in ggNMOS Devices Under ESD Condition Revisited

Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures

On the Electrostatic Discharge Robustness of Graphene

Simulation Methods for ESD Protection Development

Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?

Tunnel-field-effect-transistor based gas-sensor: Introducing gas detection with a quantum-mechanical transducer

An Island Drain Double-Gate DeMOS With Self-Aligned Sub-Gate to Achieve Multifold Transient Frequency Enhancement

Physical Insights Into the ESD Behavior of Drain Extended FinFETs (DeFinFETs) and Unique Current Filament Dynamics

Modular Measurement System for System-Efficient ESD Design on System and Component Level

Reliability aspects of gate oxide under ESD pulse stress

Design for ESD protection at its limits

Device, Circuit, and Reliability Assessment of Drain-Extended FinFETs for Sub-14 nm System on Chip Applications

Impact-ionization field-effect-transistor based biosensors for ultra-sensitive detection of biomolecules

IC Pin Modeling and Mitigation of ESD-Induced Soft Failures

A Tunnel FET for V DD Scaling Below 0.6 V With a CMOS-Comparable Performance

A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable Performance

Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability

Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs

A Systematic Method to Characterize the Soft-Failure Susceptibility of the I/Os on an Integrated Circuit Due to Electrostatic Discharge

Challenges & Physical Insights Into the Design of Fin-Based SCRs and a Novel Fin-SCR for Efficient On-Chip ESD Protection

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Advanced simulation methods for ESD protection development

Identification of Soft Failure Mechanisms Triggered by ESD Stress on a Powered USB 3.0 Interface

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

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