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Automotive Architecture Topologies: Analysis for Safety-Critical Autonomous Vehicle Applications

IEEE access, 2021, Vol.9, p.62837-62846

2021

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Run-Time Recovery and Failure Analysis of Time-Triggered Traffic in Time Sensitive Networks

IEEE access, 2021, Vol.9, p.91710-91722

2021

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Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Journal of electronic testing, 2021-04, Vol.37 (2), p.161-189

2021

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Interface Modeling for Quality and Resource Management

Logical methods in computer science, 2021-05, Vol.17, Issue 2

2021

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CompROS: A composable ROS2 based architecture for real-time embedded robotic development

2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2021, p.6449-6455

2021

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Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-Offs

1, 2016

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Networks on Chips

2006

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dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

IEEE transactions on computers, 2014-03, Vol.63 (3), p.583-594

2014

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The aethereal network on chip after ten years: goals, evolution, lessons, and future

Design Automation Conference, 2010, p.306-311

2010

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Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

VLSI Design, 2007-01, Vol.2007, p.222-231

2007

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Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

IEEE transactions on circuits and systems. I, Regular papers, 2023-12, Vol.70 (12), p.5468-5481

2023

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Decentralized Configuration of TSCH-Based IoT Networks for Distinctive QoS: A Deep Reinforcement Learning Approach

IEEE internet of things journal, 2023-10, Vol.10 (19), p.1-1

2023

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A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

VLSI Design, 2007-01, Vol.2007, p.108-123

2007

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Topology Management and TSCH Scheduling for Low-Latency Convergecast in In-Vehicle WSNs

IEEE transactions on industrial informatics, 2019-02, Vol.15 (2), p.1082-1093

2019

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A Generic Method for a Bottom-Up ASIL Decomposition

Computer Safety, Reliability, and Security, p.12-26

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Coexistence Analysis of Co-Located BLE and IEEE 802.15.4 TSCH Networks

IEEE sensors journal, 2021-08, Vol.21 (15), p.17360-17372

2021

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Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.479-492

2016

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NPTSN: RL-Based Network Planning with Guaranteed Reliability for In-Vehicle TSSDN

2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2023, p.55-66

2023

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Run-time power-down strategies for real-time SDRAM memory controllers

DAC Design Automation Conference 2012, 2012, p.988-993

2012

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SynAVB: Route and Slope Synthesis Ensuring Guaranteed Service in Ethernet AVB

2022 IEEE 27th International Conference on Emerging Technologies and Factory Automation (ETFA), 2022, p.1-8

2022

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Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms

ACM transactions on design automation of electronic systems, 2019-06, Vol.24 (3), p.1-26

2019

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Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

IEEE transactions on computers, 2016-06, Vol.65 (6), p.1882-1895

2016

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Dependable Interference-Aware Time-Slotted Channel Hopping for Wireless Sensor Networks

ACM transactions on sensor networks, 2018-03, Vol.14 (1), p.1-35

2018

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Run-time Per-Class Routing of AVB Flows in In-Vehicle TSN via Composable Delay Analysis

2022 IEEE 95th Vehicular Technology Conference: (VTC2022-Spring), 2022, p.1-7

2022

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T-CREST: Time-predictable multi-core architecture for embedded systems

Journal of systems architecture, 2015-10, Vol.61 (9), p.449-471

2015

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Automotive Architecture Topologies: Analysis for Safety-Critical Autonomous Vehicle Applications

Run-Time Recovery and Failure Analysis of Time-Triggered Traffic in Time Sensitive Networks

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality

Interface Modeling for Quality and Resource Management

CompROS: A composable ROS2 based architecture for real-time embedded robotic development

Memory Controllers for Mixed-Time-Criticality Systems: Architectures, Methodologies and Trade-Offs

Networks on Chips

dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up

The aethereal network on chip after ten years: goals, evolution, lessons, and future

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

Decentralized Configuration of TSCH-Based IoT Networks for Distinctive QoS: A Deep Reinforcement Learning Approach

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

Topology Management and TSCH Scheduling for Low-Latency Convergecast in In-Vehicle WSNs

A Generic Method for a Bottom-Up ASIL Decomposition

Coexistence Analysis of Co-Located BLE and IEEE 802.15.4 TSCH Networks

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

NPTSN: RL-Based Network Planning with Guaranteed Reliability for In-Vehicle TSSDN

Run-time power-down strategies for real-time SDRAM memory controllers

SynAVB: Route and Slope Synthesis Ensuring Guaranteed Service in Ethernet AVB

Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling

Dependable Interference-Aware Time-Slotted Channel Hopping for Wireless Sensor Networks

Run-time Per-Class Routing of AVB Flows in In-Vehicle TSN via Composable Delay Analysis

T-CREST: Time-predictable multi-core architecture for embedded systems

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