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Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective

IEEE transactions on very large scale integration (VLSI) systems, 2008-02, Vol.16 (2), p.144-155

2008

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Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-10, Vol.25 (10), p.1950-1968

2006

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Bioreactors for Connective Tissue Engineering: Design and Monitoring Innovations

Advances in biochemical engineering, biotechnology, 2009, Vol.112, p.81

2009

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The bactericidal effect of TiO2 photocatalysis involves adsorption onto catalyst and the loss of membrane integrity

FEMS microbiology letters, 2006-05, Vol.258 (1), p.18-24

2006

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A co-design approach for embedded system modeling and code generation with UML and MARTE

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.226-231

2009

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Accuracy evaluation of GEM5 simulator system

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-7

2012

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A codesign back-end approach for embedded system design

ACM transactions on design automation of electronic systems, 2000-07, Vol.5 (3), p.492-509

2000

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Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation

2011 Design, Automation & Test in Europe, 2011, p.1-4

2011

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Using genetic algorithms to map hard real-time on NoC-based systems

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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Reconfigurable Security Support for Embedded Systems

Proceedings of the 39th Annual Hawaii International Conference on System Sciences (HICSS'06), 2006, Vol.10, p.250a-250a

2006

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A reconfigurable Crypto Sub System for the Software Communication Architecture

MILCOM 2009 - 2009 IEEE Military Communications Conference, 2009, p.1-7

2009

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Communication Costs Driven Design Space Exploration for Reconfigurable Architectures

Field Programmable Logic and Application, 2003, p.921-933

2003

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A RTRM proposal for multi/many-core platforms and reconfigurable applications

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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Software Radio and Dynamic Reconfiguration on a DSP/FPGA platform

Frequenz, 2004, Vol.58 (5-6)

2004

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Configurable Computing for High-Security/High-Performance Ambient Systems

Embedded Computer Systems: Architectures, Modeling, and Simulation, 2005, Vol.3553/2005, p.72-81

2005

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Designing formal reconfiguration control using UML/MARTE

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systems

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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Power management techniques in an FPGA-based WSN node for high performance applications

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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Automatic run-time manager generation for reconfigurable MPSoC architectures

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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Fast spiking neural network architecture for low-cost FPGA devices

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-6

2012

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A heterogeneous modules interconnection architecture for FPGA-based partial dynamic reconfiguration

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-7

2012

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MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-8

2012

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Transport layer aware design of network interface in many-core systems

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-7

2012

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Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform accelerators

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012, p.1-4

2012

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Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective

Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations

Bioreactors for Connective Tissue Engineering: Design and Monitoring Innovations

The bactericidal effect of TiO2 photocatalysis involves adsorption onto catalyst and the loss of membrane integrity

A co-design approach for embedded system modeling and code generation with UML and MARTE

Accuracy evaluation of GEM5 simulator system

A codesign back-end approach for embedded system design

Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation

Using genetic algorithms to map hard real-time on NoC-based systems

Reconfigurable Security Support for Embedded Systems

A reconfigurable Crypto Sub System for the Software Communication Architecture

Communication Costs Driven Design Space Exploration for Reconfigurable Architectures

A RTRM proposal for multi/many-core platforms and reconfigurable applications

Software Radio and Dynamic Reconfiguration on a DSP/FPGA platform

Configurable Computing for High-Security/High-Performance Ambient Systems

Designing formal reconfiguration control using UML/MARTE

MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systems

Power management techniques in an FPGA-based WSN node for high performance applications

Automatic run-time manager generation for reconfigurable MPSoC architectures

Fast spiking neural network architecture for low-cost FPGA devices

A heterogeneous modules interconnection architecture for FPGA-based partial dynamic reconfiguration

MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs

Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system

Transport layer aware design of network interface in many-core systems

Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform accelerators

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