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Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.502-509

2017

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Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Journal of low power electronics and applications, 2024-01, Vol.14 (1), p.2

2024

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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-On-Chip

1, 2017

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Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

IEEE access, 2021, Vol.9, p.105831-105840

2021

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Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

IEEE access, 2019, Vol.7, p.27641-27649

2019

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Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

IEEE access, 2021, Vol.9, p.91764-91776

2021

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Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Journal of low power electronics and applications, 2013-04, Vol.3 (2), p.54-72

2013

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A 7T Security Oriented SRAM Bitcell

IEEE transactions on circuits and systems. II, Express briefs, 2019-08, Vol.66 (8), p.1396-1400

2019

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A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

IEEE transactions on circuits and systems. I, Regular papers, 2018-04, Vol.65 (4), p.1245-1256

2018

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Gain-Cell Embedded DRAM-Based Physical Unclonable Function

IEEE transactions on circuits and systems. I, Regular papers, 2018-12, Vol.65 (12), p.4208-4218

2018

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A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

IEEE transactions on very large scale integration (VLSI) systems, 2016-08, Vol.24 (8), p.2622-2633

2016

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Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation

IEEE transactions on circuits and systems. II, Express briefs, 2017-12, Vol.64 (12), p.1362-1366

2017

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Gain-Cell Embedded DRAMs: Modeling and Design Space

IEEE transactions on very large scale integration (VLSI) systems, 2020-03, Vol.28 (3), p.646-659

2020

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GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

IEEE transactions on circuits and systems. II, Express briefs, 2019-12, Vol.66 (12), p.2042-2046

2019

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Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.2180-2184, Article 2180

2018

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Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

IEEE transactions on circuits and systems. I, Regular papers, 2020-04, Vol.67 (4), p.1207-1217

2020

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Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.358-362

2016

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Single-Event Upset Tolerance Study of a Low-Voltage 13T Radiation-Hardened SRAM Bitcell

IEEE transactions on nuclear science, 2020-08, Vol.67 (8), p.1803-1812

2020

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Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

IEEE transactions on circuits and systems. II, Express briefs, 2014-04, Vol.61 (4), p.259-263

2014

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An 800-MHz Mixed- V} 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

IEEE journal of solid-state circuits, 2018-07, Vol.53 (7), p.2136-2148

2018

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A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

IEEE solid-state circuits letters, 2020, Vol.3, p.110-113

2020

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A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

IEEE solid-state circuits letters, 2023, Vol.6, p.13-16

2023

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GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-1

2020

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Gain-Cell Embedded DRAMs: Modeling and Design Space

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-1

2020

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Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-On-Chip

Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

A 7T Security Oriented SRAM Bitcell

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

Gain-Cell Embedded DRAM-Based Physical Unclonable Function

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation

Gain-Cell Embedded DRAMs: Modeling and Design Space

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Single-Event Upset Tolerance Study of a Low-Voltage 13T Radiation-Hardened SRAM Bitcell

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

An 800-MHz Mixed- V} 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Gain-Cell Embedded DRAMs: Modeling and Design Space

Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique

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