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A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1197-1206

2021

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A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback

IEEE transactions on circuits and systems. II, Express briefs, 2021-05, Vol.68 (5), p.1645-1649

2021

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Target classification scheme using phase characteristics for automotive FMCW radar

Electronics letters, 2016-12, Vol.52 (25), p.2061-2063

2016

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A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier

IEEE transactions on circuits and systems. II, Express briefs, 2019-07, Vol.66 (7), p.1119-1123

2019

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Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC's

IEEE transactions on circuits and systems. I, Regular papers, 2018-10, Vol.65 (10), p.3227-3240

2018

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An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

Journal of semiconductor technology and science, 2023-04, Vol.23 (2), p.118-127

2023

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A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2009-05, Vol.56 (5), p.894-901

2009

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High-efficiency low-noise pulse-width modulation DC–DC buck converter based on multi-partition switching for mobile system-on-a-chip applications

IET power electronics, 2016-03, Vol.9 (3), p.559-567

2016

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A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp

IEEE journal of solid-state circuits, 2010-03, Vol.45 (3), p.620-628

2010

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A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2398-2407

2005

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A 12-bit 180 MS/s Current-steering DAC with Cascaded Local-element Matching Topologies

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2020, 20(1), 91, pp.99-104

2020

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A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

IEEE transactions on circuits and systems. II, Express briefs, 2011-05, Vol.58 (5), p.274-278

2011

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A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

IEEE journal of solid-state circuits, 2008-05, Vol.43 (5), p.1195-1206

2008

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Area-efficient Ramp Signal-based Column Driving Technique for AMOLED Panels

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2019, 19(4), 88, pp.347-356

2019

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A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

IEEE transactions on circuits and systems. II, Express briefs, 2023-02, Vol.70 (2), p.1-1

2023

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A 1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(3), 81, pp.346-351

2018

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Analog Front-end for EMG Acquisition System

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(6), 84, pp.667-676

2018

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A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2772-2782

2018

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A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.960-969

2005

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A 19.5 ps-LSB Vernier-type Time-to-digital Converter for PET

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(6), 78, pp.800-805

2017

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Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2005-01, Vol.52 (1), p.1-12

2005

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A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2nd Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2023, 23(5), 113, pp.265-272

2023

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Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(1), 67, pp.70-79

2016

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A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, 14(2), 56, pp.189-197

2014

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A Non-binary C-R Hybrid DAC for 12 b 100 MS/s CMOS SAR ADCs with Fast Residue Settling

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2021, 21(4), 100, pp.255-262

2021

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A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications

A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback

Target classification scheme using phase characteristics for automotive FMCW radar

A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier

Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC's

An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration

High-efficiency low-noise pulse-width modulation DC–DC buck converter based on multi-partition switching for mobile system-on-a-chip applications

A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A 12-bit 180 MS/s Current-steering DAC with Cascaded Local-element Matching Topologies

A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

Area-efficient Ramp Signal-based Column Driving Technique for AMOLED Panels

A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

A 1.0 V 77.5 dB Dynamic Range Delta-sigma ADC using Op-Amp Bias Sharing Technique

Analog Front-end for EMG Acquisition System

A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

A 19.5 ps-LSB Vernier-type Time-to-digital Converter for PET

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

A 97.7-dB DR 12.3-μW 1-kHz Bandwidth 2nd Order Delta-sigma Modulator with a Fully Differential Class-AB Op-Amp using Floating Class-AB Control

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

A Non-binary C-R Hybrid DAC for 12 b 100 MS/s CMOS SAR ADCs with Fast Residue Settling

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