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SAT-Based Scalable Formal Verification Solutions

1. Aufl., 2007

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Efficient SAT-based bounded model checking for software verification

Theoretical computer science, 2008-09, Vol.404 (3), p.256-274

2008

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Sat-based verification methods and applications in hardware verification

Lecture notes in computer science, 2006, p.108-143

2006

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Circuit-based Boolean Reasoning

Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation, 2001, p.232-237

2001

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Enhancing simulation with BDDs and ATPG

Proceedings - ACM IEEE Design Automation Conference, 1999, p.385-390

1999

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Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.747-750

2002

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Efficient distributed SAT and SAT-based distributed Bounded Model Checking

International journal on software tools for technology transfer, 2006-08, Vol.8 (4-5), p.387-396

2006

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Robust Boolean reasoning for equivalence checking and functional property verification

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-12, Vol.21 (12), p.1377-1394

2002

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Localization and Register Sharing for Predicate Abstraction

Lecture notes in computer science, 2005, p.397-412

2005

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SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver

Lecture notes in computer science, 2006, p.135-150

2006

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DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems

Lecture notes in computer science, 2005, p.575-580

2005

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Verification of Embedded Memory Systems using Efficient Memory Modeling

Design, Automation and Test in Europe, 2005, p.1096-1101

2005

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Efficient Modeling of Embedded Memories in Bounded Model Checking

Computer Aided Verification, 2004, p.440-452

2004

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Scalable and precise symbolic analysis for atomicity violations

2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011), 2011, p.123-132

Ganai, Malay K.

2011

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Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking

Correct Hardware Design and Verification Methods, 2003, p.334-347

2003

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Beyond safety: customized SAT-based model checking

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.738-743

2005

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Dynamic Livelock Analysis of Multi-threaded Programs

Runtime Verification, p.3-18

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Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT(\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$\mathcal{LIA}$\end{document})

Hardware and Software: Verification and Testing, p.68-83

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Interval Analysis for Concurrent Trace Programs Using Transaction Sequence Graphs

Runtime Verification, p.253-269

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Runtime Verification: Third International Conference, RV 2012, Istanbul, Turkey, September 25-28, 2012, Revised Selected Papers

2013, 2013

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Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002, p.747-750

2002

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Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-08, Vol.27 (8), p.1513-1517

2008

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d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework

Hardware and Software: Verification and Testing, p.194-199

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Efficient SAT-based unbounded symbolic model checking using circuit cofactoring

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.510-517

2004

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Efficient BMC for Multi-Clock Systems with Clocked Specifications

2007 Asia and South Pacific Design Automation Conference, 2007, p.310-315

2007

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