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Ultralow‐Power Compact Artificial Synapse Based on a Ferroelectric Fin Field‐Effect Transistor for Spatiotemporal Information Processing

Advanced intelligent systems, 2023-11, Vol.5 (11), p.n/a

2023

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A Three-Dimensional Simulation Study of the Novel Comb-Like-Channel Field-Effect Transistors for the 5-nm Technology Node and Beyond

IEEE transactions on electron devices, 2022-09, Vol.69 (9), p.4786-4790

2022

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Phonon-assisted charge carriers thermalization in semiconductor Si and metallic silicide NiSi2, CoSi2: A non-adiabatic molecular dynamics study

Journal of applied physics, 2024-07, Vol.136 (2)

2024

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Transistor Compact Model Based on Multigradient Neural Network and Its Application in SPICE Circuit Simulations for Gate-All-Around Si Cold Source FETs

IEEE transactions on electron devices, 2021-09, Vol.68 (9), p.4181-4188

2021

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Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and Balanced Driving Currents Using Single Work Function Metal Process

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.1-7

2022

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Design and Simulation of Steep-Slope Silicon Cold Source FETs With Effective Carrier Distribution Model

IEEE transactions on electron devices, 2020-06, Vol.67 (6), p.2243-2248

2020

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Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit

IEEE transactions on electron devices, 2022-07, Vol.69 (7), p.3581-3588

2022

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The Device and Circuit Level Benchmark of Si-Based Cold Source FETs for Future Logic Technology

IEEE transactions on electron devices, 2022-06, Vol.69 (6), p.3483-3489

2022

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A Machine Learning Approach for Optimization of Channel Geometry and Source/Drain Doping Profile of Stacked Nanosheet Transistors

IEEE transactions on electron devices, 2022-07, Vol.69 (7), p.3568-3574

2022

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Endurance Characteristics of Negative Capacitance FinFETs With Negligible Hysteresis

IEEE electron device letters, 2021-02, Vol.42 (2), p.260-263

2021

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Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.6095-6101

2022

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A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET

IEEE transactions on electron devices, 2021-11, Vol.68 (11), p.5455-5461

2021

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Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic \textit -and \textit -Values

IEEE transactions on electron devices, 2022, p.1-7

2022

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Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current

Materials science in semiconductor processing, 2022-03, Vol.140, p.106337, Article 106337

2022

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Analog Monolayer MoS2 Transistor with Record-high Intrinsic Gain (>100 dB) and Ultra-low Saturation Voltage (<0.1 V) by Source Engineering

2021 Symposium on VLSI Technology, 2021, p.1-2

2021

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Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors

Microelectronics, 2023-11, Vol.141, p.105970, Article 105970

2023

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Prediction of Key Metrics of Stacked Nanosheet nFETs using Genetic Algorithm-based Neural Networks

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2022, p.3-4

2022

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Investigation on negative capacitance FinEFT beyond 7 nm node from device to circuit

Microelectronics, 2021-10, Vol.116, p.105196, Article 105196

2021

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Device-Circuit Co-Optimization for Negative Capacitance FinFETs based on SPICE Model

2020 International Workshop on Advanced Patterning Solutions (IWAPS), 2020, p.1-4

2020

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Multi-Physics Evaluation of Silicon Steep-Slope Cold Source FET

2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021, p.1-3

2021

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A Multi-physics TCAD Framework for Fast and Accurate Simulation of SteepSlope Si-based Cold Source FET

2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020, p.66-67

2020

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Rural Credit Constraint and Informal Rural Credit Accessibility in China

Sustainability, 2019-04, Vol.11 (7), p.1935

2019

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The decision to buy genetically modified foods in China: what makes the difference?

Environment, development and sustainability, 2024-06, Vol.26 (6), p.15213-15235

2024

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Credit Constraints on Farm Household Welfare in Rural China: Evidence from Fujian Province

Sustainability, 2019-06, Vol.11 (11), p.3221

2019

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Homeownership in urban China: an empirical study of borrower characteristics and the Housing Provident Fund program in Kunming

Journal of Asia business studies, 2018-08, Vol.12 (3), p.318-339

2018

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Ultralow‐Power Compact Artificial Synapse Based on a Ferroelectric Fin Field‐Effect Transistor for Spatiotemporal Information Processing

A Three-Dimensional Simulation Study of the Novel Comb-Like-Channel Field-Effect Transistors for the 5-nm Technology Node and Beyond

Phonon-assisted charge carriers thermalization in semiconductor Si and metallic silicide NiSi2, CoSi2: A non-adiabatic molecular dynamics study

Transistor Compact Model Based on Multigradient Neural Network and Its Application in SPICE Circuit Simulations for Gate-All-Around Si Cold Source FETs

Novel Channel-First Fishbone FETs With Symmetrical Threshold Voltages and Balanced Driving Currents Using Single Work Function Metal Process

Design and Simulation of Steep-Slope Silicon Cold Source FETs With Effective Carrier Distribution Model

Investigation of Novel Hybrid Channel Complementary FET Scaling Beyond 3-nm Node From Device to Circuit

The Device and Circuit Level Benchmark of Si-Based Cold Source FETs for Future Logic Technology

A Machine Learning Approach for Optimization of Channel Geometry and Source/Drain Doping Profile of Stacked Nanosheet Transistors

Endurance Characteristics of Negative Capacitance FinFETs With Negligible Hysteresis

Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic - and -Values

A Multiscale Simulation Framework for Steep-Slope Si Nanowire Cold Source FET

Layout Optimization of Complementary FET 6T-SRAM Cell Based on a Universal Methodology Using Sensitivity With Respect to Parasitic \textit -and \textit -Values

Scallop-shaped p-type FinFETs with improved short-channel effects immunity and driving current

Analog Monolayer MoS2 Transistor with Record-high Intrinsic Gain (>100 dB) and Ultra-low Saturation Voltage (<0.1 V) by Source Engineering

Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors

Prediction of Key Metrics of Stacked Nanosheet nFETs using Genetic Algorithm-based Neural Networks

Investigation on negative capacitance FinEFT beyond 7 nm node from device to circuit

Device-Circuit Co-Optimization for Negative Capacitance FinFETs based on SPICE Model

Multi-Physics Evaluation of Silicon Steep-Slope Cold Source FET

A Multi-physics TCAD Framework for Fast and Accurate Simulation of SteepSlope Si-based Cold Source FET

Rural Credit Constraint and Informal Rural Credit Accessibility in China

The decision to buy genetically modified foods in China: what makes the difference?

Credit Constraints on Farm Household Welfare in Rural China: Evidence from Fujian Province

Homeownership in urban China: an empirical study of borrower characteristics and the Housing Provident Fund program in Kunming

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