UB Paderborn / Katalog / Suche / in CDI

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

IEEE journal of solid-state circuits, 2010-12, Vol.45 (12), p.2634-2646

2010

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IEEE_Xplore

Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs

IEEE transactions on circuits and systems. I, Regular papers, 2023-11, Vol.70 (11), p.1-14

2023

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IEEE_Xplore

Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2007-03, Vol.54 (3), p.492-503

2007

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IEEE_Xplore

MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2020-09, Vol.67 (9), p.3084-3098

2020

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IEEE_Xplore

The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs

IEEE transactions on circuits and systems. I, Regular papers, 2017-01, Vol.64 (1), p.14-23

2017

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IEEE_Xplore

Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs

IEEE transactions on circuits and systems. I, Regular papers, 2018-02, Vol.65 (2), p.421-433

2018

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IEEE_Xplore

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

IEEE transactions on circuits and systems. I, Regular papers, 2019-01, Vol.66 (1), p.1-19

2019

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IEEE_Xplore

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

IEEE journal of solid-state circuits, 2015-02, Vol.50 (2), p.450-463

2015

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IEEE_Xplore

Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs

IEEE transactions on circuits and systems. I, Regular papers, 2019-08, Vol.66 (8), p.2843-2853

2019

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IEEE_Xplore

Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional- N PLLs

IEEE transactions on circuits and systems. I, Regular papers, 2016-06, Vol.63 (6), p.836-847

2016

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IEEE_Xplore

An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.465-479

2022

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IEEE_Xplore

Why Dynamic-Element-Matching DACs Work

IEEE transactions on circuits and systems. II, Express briefs, 2010-02, Vol.57 (2), p.69-74

Galton, I.

2010

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IEEE_Xplore

A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error

IEEE journal of solid-state circuits, 2019-08, Vol.54 (8), p.2219-2229

2019

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IEEE_Xplore

A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones

IEEE transactions on signal processing, 2013-08, Vol.61 (16), p.4172-4180

2013

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IEEE_Xplore

A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.983-995

2013

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IEEE_Xplore

Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO" [Feb 15 450-463]

IEEE journal of solid-state circuits, 2015-09, Vol.50 (9), p.2224-2224

2015

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IEEE_Xplore

DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional- N PLLs

IEEE transactions on circuits and systems. I, Regular papers, 2022-12, Vol.69 (12), p.1-14

2022

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IEEE_Xplore

Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional- [Formula Omitted] PLLs

IEEE transactions on circuits and systems. I, Regular papers, 2016-06, Vol.63 (6), p.836

2016

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Verfügbarkeit prüfen

Delta-Sigma FDC Based Fractional-N PLLs

IEEE transactions on circuits and systems. I, Regular papers, 2013-05, Vol.60 (5), p.1274-1285

2013

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IEEE_Xplore

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

IEEE journal of solid-state circuits, 2015-12, Vol.50 (12), p.2988-3002

2015

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Verfügbarkeit prüfen

Quantization Noise Cancellation for FDC-Based Fractional- N PLLs

IEEE transactions on circuits and systems. II, Express briefs, 2015-12, Vol.62 (12), p.1119-1123

2015

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IEEE_Xplore

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs

IEEE transactions on circuits and systems. I, Regular papers, 2018-10, Vol.65 (10), p.3125-3137

2018

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IEEE_Xplore

Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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IEEE_Xplore

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL

IEEE journal of solid-state circuits, 2021-09, Vol.56 (9), p.2711-2723

2021

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IEEE_Xplore

A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3314-3328

2009

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IEEE_Xplore

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Weitere Dienste

Einstellungen

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs

Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators

MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration

The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs

Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO

Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs

Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional- N PLLs

An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs

Why Dynamic-Element-Matching DACs Work

A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error

A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones

A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB

Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO" [Feb 15 450-463]

DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional- N PLLs

Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional- [Formula Omitted] PLLs

Delta-Sigma FDC Based Fractional-N PLLs

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

Quantization Noise Cancellation for FDC-Based Fractional- N PLLs

Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs

Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs

A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL

A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction

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