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A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.114-116

2018

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Deeper SSC estimator used as CDR

Electronics letters, 2013-05, Vol.49 (11), p.691-692

2013

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A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-4

2018

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A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3547-3559

2009

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A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.333-336

2015

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A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.19-28

2024

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Pin-efficient 9-bit 8-wire 4-level synergetic-equalisation coding scheme for 216 Gb/s PAM4 transceiver

Electronics letters, 2020-05, Vol.56 (11), p.548-550

2020

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A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.341-344

2015

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SSC tracking analysis and a deeper-SSC estimator

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.1408-1411

2013

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A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.2690-2693

2013

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Digitally tuned degeneration resistance to improve linearity of boost factors for analogue equalisers

Electronics letters, 2015-05, Vol.51 (10), p.745-747

2015

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Power-efficient pre-emphasis method for transmitters with LVDS drivers

Electronics letters, 2014-11, Vol.50 (24), p.1811-1813

2014

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40 Gbps 4-level pulse amplitude modulation closed-loop decision-feedback equaliser with high-speed comparator in 55 nm CMOS technology

Electronics letters, 2018-06, Vol.54 (12), p.741-742

2018

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A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.2464-2467

2013

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A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.1-12

2023

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Hardware-efficient slope-error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver

Electronics letters, 2018-08, Vol.54 (17), p.1020-1022

2018

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Wearable Tape-Based Smart Biosensing Systems for Lactate and Glucose

IEEE sensors journal, 2020-04, Vol.20 (7), p.3757-3765

2020

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A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.1-11

2023

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Deeper SSC estimator used as CDR

Electronics letters, 2013-05, Vol.49 (11), p.1-1

2013

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Swing-programmable SST transmitter with power-efficient de-emphasis

Electronics letters, 2015-06, Vol.51 (12), p.901-902

2015

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6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.112-114

2023

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A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC

Circuits, systems, and signal processing, 2022-12, Vol.41 (12), p.6694-6708

2022

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A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.2487-2490

2022

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Closed-Loop Diabetes Minipatch Based on a Biosensor and an Electroosmotic Pump on Hollow Biodegradable Microneedles

ACS sensors, 2022-05, Vol.7 (5), p.1347-1360

2022

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A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS

Deeper SSC estimator used as CDR

A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis

A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS

Pin-efficient 9-bit 8-wire 4-level synergetic-equalisation coding scheme for 216 Gb/s PAM4 transceiver

A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis

SSC tracking analysis and a deeper-SSC estimator

A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning

Digitally tuned degeneration resistance to improve linearity of boost factors for analogue equalisers

Power-efficient pre-emphasis method for transmitters with LVDS drivers

40 Gbps 4-level pulse amplitude modulation closed-loop decision-feedback equaliser with high-speed comparator in 55 nm CMOS technology

A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL

A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS

Hardware-efficient slope-error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver

Wearable Tape-Based Smart Biosensing Systems for Lactate and Glucose

A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS

Deeper SSC estimator used as CDR

Swing-programmable SST transmitter with power-efficient de-emphasis

6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS

A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC

A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications

Closed-Loop Diabetes Minipatch Based on a Biosensor and an Electroosmotic Pump on Hollow Biodegradable Microneedles

A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET

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