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New approach for improving the performance of dual axis solar tracker with auto cleaning system

Soft computing (Berlin, Germany), 2023-12, Vol.27 (24), p.18765-18773

2023

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Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

Analog integrated circuits and signal processing, 2019-07, Vol.100 (1), p.61-77

2019

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Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

Wireless personal communications, 2019-10, Vol.108 (4), p.2311-2339

2019

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Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay

Journal of ambient intelligence and humanized computing, 2022-09, Vol.13 (9), p.4559-4568

2022

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Proposed Design of 1 KB Memory Array Structure for Cache Memories

Wireless personal communications, 2019-11, Vol.109 (2), p.823-847

2019

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Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies

Wireless personal communications, 2022-08, Vol.125 (3), p.2239-2251

2022

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Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

Wireless personal communications, 2019, Vol.108 (4), p.2311-2339

2019

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Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Wireless personal communications, 2023-03, Vol.129 (1), p.37-55

2023

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Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Wireless personal communications, 2023, Vol.128 (2), p.1417-1435

2023

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A Variant of Long Multiplication Design with Low Power and Area Using Modified 7:3 Compressor for Biomedical Applications

Wireless personal communications, 2022-12, Vol.127 (4), p.3299-3319

2022

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A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

Wireless personal communications, 2022-05, Vol.124 (2), p.1297-1315

2022

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A novel design and implementation of IoT based real-time ATM surveillance and security system

Advances in computational intelligence, 2022-02, Vol.2 (1), p.1, Article 1

2022

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Design of Efficient Low Power Stable 4-Bit Memory Cell

International journal of computer applications, 2013-01, Vol.84 (1), p.9-13

2013

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Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

International journal of computer applications, 2019-01, Vol.182 (36), p.1-5

2019

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Surgical management of windblown hand: Results and literature review

Journal of children's orthopaedics, 2009-04, Vol.3 (2), p.109-114

2009

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Implementation of Sobel operator based image edge detection on FPGA

Materials today : proceedings, 2021, Vol.45, p.2401-2407

2021

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Development of LPG Leakage Detection Alert and Auto Exhaust System using IoT

2021 7th International Conference on Electrical Energy Systems (ICEES), 2021, p.558-563

2021

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Design of Reconfigurable Signed Dual Modulo Multiplier Function (DMMF) for RNS

2021 Smart Technologies, Communication and Robotics (STCR), 2021, p.1-5

2021

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Low Power Design of 4-bit Simultaneous Counter using Digital Switching Circuits for Low Range Counting Applications

2020 5th International Conference on Devices, Circuits and Systems (ICDCS), 2020, p.316-320

2020

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Design and Analysis of 8-Bit Stable SRAM for Ultra Low Power Applications

2020 5th International Conference on Devices, Circuits and Systems (ICDCS), 2020, p.221-225

2020

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Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology

International journal of computer applications, 2016-06, Vol.144 (2), p.1-4

2016

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Design of Novel SRAM cell using Hybrid VLSI Techniques for Low Power and High Speed in Embedded Memories

2018 International Conference on Intelligent Computing and Communication for Smart World (I2C2SW), 2018, p.22-32

2018

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Functional verification environment for I2C master controller using system verilog

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN), 2017, p.1-6

2017

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Highly stereoselective tandem cyclizations of 5-hexenyllithiums: preparation of endo-2-substituted bicyclo[2.2.1]heptanes and 3-substituted trans-bicyclo[3.3.0]octanes

Journal of the American Chemical Society, 1992-10, Vol.114 (21), p.8053-8060

1992

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Design and verification of LTSSM in USB 3.0 link layer using system verilog

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN), 2017, p.1-6

2017

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New approach for improving the performance of dual axis solar tracker with auto cleaning system

Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits

Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay

Proposed Design of 1 KB Memory Array Structure for Cache Memories

Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies

Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

A Variant of Long Multiplication Design with Low Power and Area Using Modified 7:3 Compressor for Biomedical Applications

A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors

A novel design and implementation of IoT based real-time ATM surveillance and security system

Design of Efficient Low Power Stable 4-Bit Memory Cell

Design and Comparative Analysis of SRAM with Performance Optimization using MTCMOS Technique for High Speed Computation

Surgical management of windblown hand: Results and literature review

Implementation of Sobel operator based image edge detection on FPGA

Development of LPG Leakage Detection Alert and Auto Exhaust System using IoT

Design of Reconfigurable Signed Dual Modulo Multiplier Function (DMMF) for RNS

Low Power Design of 4-bit Simultaneous Counter using Digital Switching Circuits for Low Range Counting Applications

Design and Analysis of 8-Bit Stable SRAM for Ultra Low Power Applications

Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology

Design of Novel SRAM cell using Hybrid VLSI Techniques for Low Power and High Speed in Embedded Memories

Functional verification environment for I2C master controller using system verilog

Highly stereoselective tandem cyclizations of 5-hexenyllithiums: preparation of endo-2-substituted bicyclo[2.2.1]heptanes and 3-substituted trans-bicyclo[3.3.0]octanes

Design and verification of LTSSM in USB 3.0 link layer using system verilog

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