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Photonic Reconfigurable Accelerators for Efficient Inference of CNNs with Mixed-Sized Tensors

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1

2022

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DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-09, Vol.37 (9), p.1760-1773

2018

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Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-05, Vol.40 (5), p.850-863

2021

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LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip

IEEE transactions on multi-scale computing systems, 2018-10, Vol.4 (4), p.758-772

2018

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Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration

2020 IEEE 38th International Conference on Computer Design (ICCD), 2020, p.417-420

2020

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SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures

Proceedings of the 55th Annual Design Automation Conference, 2018, p.1-6

2018

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ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021, p.200-205

2021

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PICO: Mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016, p.104-109

2016

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A plastic total internal reflection photoluminescence device for enzymatic biosensing

Lab on a chip, 2013-12, Vol.13 (24), p.4775-4783

2013

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HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs

IEEE transactions on very large scale integration (VLSI) systems, 2018-01, Vol.26 (1), p.168-181

2018

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An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects

ACM journal on emerging technologies in computing systems, 2024-04, Vol.20 (2), p.1-34, Article 6

2024

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Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit

Proceedings of the 19th ACM Conference on Embedded Networked Sensor Systems, 2021, p.628-634

2021

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Work-in-Progress: Mitigating Inter-Channel Crosstalk Non-Uniformity in Microring Filter Arrays of Photonic NoCs

2019 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2019, p.1-2

2019

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Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling

2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2017, p.1-8

2017

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DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency

2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), 2017, p.41-46

2017

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3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead

IEEE transactions on multi-scale computing systems, 2015-07, Vol.1 (3), p.168-184

2015

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Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling

2018 Ninth International Green and Sustainable Computing Conference (IGSC), 2018, p.1-7

2018

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3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.1-7

2014

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Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study

ACM journal on emerging technologies in computing systems, 2022-07, Vol.18 (3), p.1-36, Article 45

2022

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Work-in-Progress: Mitigating Write Disturbance in Phase Change Memory Architectures

2019 International Conference on Compliers, Architectures and Synthesis for Embedded Systems (CASES), 2019, p.1-2

2019

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Work-in-Progress: A Scalable Stochastic Number Generator for Phase Change Memory Based In-Memory Stochastic Processing

2019 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2019, p.1-2

2019

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Securing Photonic NoC Architectures from Hardware Trojans

2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018, p.1-8

2018

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Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling

2016 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2016, p.1-10

2016

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Low-Latency, Energy-Efficient In-DRAM CNN Acceleration with Bit-Parallel Unary Computing

Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, p.393-409

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Photonic Reconfigurable Accelerators for Efficient Inference of CNNs with Mixed-Sized Tensors

DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance

Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks

LIBRA: Thermal and Process Variation Aware Reliability Management in Photonic Networks-on-Chip

Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration

SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures

ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing

PICO: Mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs

Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures

A plastic total internal reflection photoluminescence device for enzymatic biosensing

HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs

An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects

Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit

Work-in-Progress: Mitigating Inter-Channel Crosstalk Non-Uniformity in Microring Filter Arrays of Photonic NoCs

Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling

DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency

3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead

Mitigating the Energy Impacts of VBTI Aging in Photonic Networks-on-Chip Architectures with Multilevel Signaling

3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time

Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study

Work-in-Progress: Mitigating Write Disturbance in Phase Change Memory Architectures

Work-in-Progress: A Scalable Stochastic Number Generator for Phase Change Memory Based In-Memory Stochastic Processing

Securing Photonic NoC Architectures from Hardware Trojans

Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling

Low-Latency, Energy-Efficient In-DRAM CNN Acceleration with Bit-Parallel Unary Computing

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