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Angular Dependency of Neutron-Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM

IEEE transactions on nuclear science, 2012-12, Vol.59 (6), p.2791-2795

2012

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Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.333-343

2012

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Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.255-264

2013

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Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs

2023 International Electron Devices Meeting (IEDM), 2023, p.1-4

2023

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Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM

IEEE transactions on nuclear science, 2011-08, Vol.58 (4), p.2097-2102

2011

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On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2012-10, Vol.20 (10), p.1876-1880

2012

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Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

IEEE transactions on circuits and systems. II, Express briefs, 2012-12, Vol.59 (12), p.918-921

2012

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An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion

IEEE transactions on circuits and systems. II, Express briefs, 2011-05, Vol.58 (5), p.299-303

2011

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Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V-Aware Dual Supply Voltage Technique

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1175-1179

2013

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Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.436-437

2013

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13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO

2012 IEEE International Solid-State Circuits Conference, 2012, p.486-488

2012

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Demonstrating performance improvement of complementary TFET circuits by Ion enhancement based on isoelectronic trap technology

2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.19.4.1-19.4.4

2016

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Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM

2010 IEEE International Reliability Physics Symposium, 2010, p.213-217

2010

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Adaptive performance compensation with on-chip variation monitoring

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, p.984-989

2011

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Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits

2009 IEEE Custom Integrated Circuits Conference, 2009, p.215-218

2009

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Efficiency Increase in On-Chip Buck Converter by Introduction of High Permeability Material to Inductor on Interposer

Journal of the Japan Society of Powder and Powder Metallurgy, 2014, Vol.61 (S1), p.S340-S342

2014

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Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, p.1-4

2012

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Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS

IEEE/ACM International Symposium on Low Power Electronics and Design, 2011, p.21-26

2011

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Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits

2012 IEEE International Solid-State Circuits Conference, 2012, p.308-310

2012

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CMOS Switch Buck DC-DC Converter Fabricated in Organic Interposer with Embedded Zn-Fe Ferrite Core Inductor

Journal of the Magnetics Society of Japan, 2015-03, Vol.39 (2), p.71-79

2015

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CMOS Switch Buck DC-DC Converter Fabricated in Organic Interposer with Embedded Zn-Fe Ferrite Core Inductor

Journal of the Magnetics Society of Japan, 2015/03/01, Vol.39(2), pp.71-79

2015

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1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.104-105

2013

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Fast insertion methods of a double-array structure

Software, practice & experience, 2001-01, Vol.31 (1), p.43-65

2001

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Differential Detection of MSK with Nonredundant Error Correction

I.R.E. transactions on communications systems, 1979-06, Vol.27 (6), p.912-918

1979

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Angular Dependency of Neutron-Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM

Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits

Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits

Milli-Kelvin Analysis Revealing the Role of Band-edge States in Cryogenic MOSFETs

Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM

On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V-Aware Dual Supply Voltage Technique

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO

Demonstrating performance improvement of complementary TFET circuits by Ion enhancement based on isoelectronic trap technology

Alpha-particle-induced soft errors and multiple cell upsets in 65-nm 10T subthreshold SRAM

Adaptive performance compensation with on-chip variation monitoring

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits

Efficiency Increase in On-Chip Buck Converter by Introduction of High Permeability Material to Inductor on Interposer

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS

Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits

CMOS Switch Buck DC-DC Converter Fabricated in Organic Interposer with Embedded Zn-Fe Ferrite Core Inductor

CMOS Switch Buck DC-DC Converter Fabricated in Organic Interposer with Embedded Zn-Fe Ferrite Core Inductor

1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control

Fast insertion methods of a double-array structure

Differential Detection of MSK with Nonredundant Error Correction

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